P R E L I M I N A R Y

PS010504-1002

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Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

iii

Table of Contents

Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Counter/Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Input/Output and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
User-Programmable Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pins Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Central Processing Unit (CPU) Description . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Memory (ROM and RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Clock Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Register Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Registers (Grouped by Function) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Precharacterization Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

List of Figures

Figure 1. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. 48-Pin SSOP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. 40-Pin DIP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Program Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Standard Z8 Register File (Working Reg. Groups 0F, Bank 0) . . . 12
Figure 6. Z8 Expanded Register File Architecture . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. External Interrupt Sources IRQ0IRQ2 Block Diagram . . . . . . . . . . 16
Figure 9. IRQ Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. Interrupt Request Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. General Input/Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. Analog Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 13. Active Glitch/Power Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14. I-V Characteristics for the Current Sink Pad P43 . . . . . . . . . . . . . . 29
Figure 15. T

Counter/Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 16. Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 17. Prescaler 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 18. Counter/Timer 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 19. Timer Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 20. Starting the Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 21. Counting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 22. Timer Mode Register T

OUT

Operation . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 23. Counter/Timer Output Using T

OUT

. . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 24. Internal Clock Output Using T

OUT

. . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 25. Timer Mode Register T

Operation . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 26. Prescaler 1 T

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 27. External Clock Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 28. Gated Clock Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 29. Triggered Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 30. Counter/Timer Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 31. Transmit Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 32. Demodulation Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 33. Test Load Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

List of Tables

Table 1.

Z86L972/Z86L973/Z86L94 Comparison . . . . . . . . . . . . . . . . . . . . . . 1

Table 2.

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3.

Interrupt Types, Sources, and Vectors . . . . . . . . . . . . . . . . . . . . . . 14

Table 4.

Interrupt Edge Select for External Interrupts . . . . . . . . . . . . . . . . . . 16

Table 5.

Control and Status Register Reset Conditions . . . . . . . . . . . . . . . . 19

Table 6.

Clock Status in Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 7.

Special Port Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 8.

Active Glitch/Filter Specifications (Preliminary) . . . . . . . . . . . . . . . . 27

Table 9.

Current Sink Pad P43 Specifications (Preliminary) . . . . . . . . . . . . . 28

Table 10. I/O Port Registers (Group 0, Bank 0, Registers 0F) . . . . . . . . . . . 47
Table 11. Timer Control Registers (Group 0, Bank D, Registers 0F) . . . . . . 48
Table 12. Control and Status Registers (Group F, Bank 0,

Registers 0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 13. SMR and Port Mode Registers (Group 0, Bank F,

Registers 0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 14. Register Description Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 15. FLAGS Register [Group/Bank F0h, Register C (R252)] . . . . . . . . . . 52
Table 16. RP Register [Group/Bank F0h, Register D (R253)] . . . . . . . . . . . . . 53
Table 17. SP Register [Group/Bank F0h, Register F (R255)] . . . . . . . . . . . . . 54
Table 18. LB Register (Group/Bank 0Dh, Register C) . . . . . . . . . . . . . . . . . . . 55
Table 19. IMR (Group/Bank 0Fh, Register B) . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 20. IPR (Group/Bank 0Fh, Register 9) . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 21. IRQ (Group/Bank 0Fh, Register A) . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 22. P456CON Register (Group/Bank 0Fh, Register 0) . . . . . . . . . . . . . 60
Table 23. P2 Register [Group/Bank 00h, Register 2 (R2)] . . . . . . . . . . . . . . . 61
Table 24. P2M Register [Group/Bank F0h, Register 6 (R246)] . . . . . . . . . . . . 61
Table 25. P3M Register [Group/Bank F0h, Register 7 (R247)] . . . . . . . . . . . . 61
Table 26. P4 Register [Group/Bank 00h, Register 4 (R4)] . . . . . . . . . . . . . . . 62
Table 27. P4M Register (Group/Bank 0Fh, Register 2) . . . . . . . . . . . . . . . . . . 62
Table 28. P5 Register [Group/Bank 00h, Register 5 (R5)] . . . . . . . . . . . . . . . 63
Table 29. P5M Register (Group/Bank 0Fh, Register 4) . . . . . . . . . . . . . . . . . . 63
Table 30. P6 Register [Group/Bank 00h, Register 6 (R6)] . . . . . . . . . . . . . . . 64
Table 31. P6M Register (Group/Bank 0Fh, Register 6) . . . . . . . . . . . . . . . . . . 64
Table 32. T1 Register [Group/Bank F0h, Register 2 (R242)] . . . . . . . . . . . . . 65

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

vii

Table 33. TMR Register [Group/Bank F0h, Register 1 (R241)] . . . . . . . . . . . . 65
Table 34. PRE1 Register [Group/Bank F0h, Register 3 (R243)] . . . . . . . . . . . 66
Table 35. CTR1 Register (In Transmit Mode) (Group/Bank 0Dh,

Table 36. CTR1 Register (in Demodulation Mode) (Group/Bank 0Dh,

Table 37. CTR3 Register (Group/Bank 0Dh, Register 3) . . . . . . . . . . . . . . . . . 69
Table 38. CTR0 Register (Group/Bank 0Dh, Register 0) . . . . . . . . . . . . . . . . 70
Table 39. HI8 Register (Group/Bank 0Dh, Register B) . . . . . . . . . . . . . . . . . . 71
Table 40. LO8 Register (Group/Bank 0Dh, Register A) . . . . . . . . . . . . . . . . . . 71
Table 41. TC8H Register (Group/Bank 0Dh, Register 5) . . . . . . . . . . . . . . . . 72
Table 42. TC8L Register (Group/Bank 0Dh, Register 4) . . . . . . . . . . . . . . . . . 72
Table 43. CTR2 Register (Group/Bank 0Dh, Register 2) . . . . . . . . . . . . . . . . 73
Table 44. HI16 Register (Group/Bank 0Dh, Register 9) . . . . . . . . . . . . . . . . . 74
Table 45. LO16 Register (Group/Bank 0Dh, Register 8) . . . . . . . . . . . . . . . . . 74
Table 46. TC16H Register (Group/Bank 0Dh, Register 7) . . . . . . . . . . . . . . . 75
Table 47. TC16L Register (Group/Bank 0Dh, Register 6) . . . . . . . . . . . . . . . . 75
Table 48. SMR Register (Group/Bank 0Fh, Register B) . . . . . . . . . . . . . . . . . 76
Table 49. P2SMR Register (Group/Bank 0Fh, Register 1) . . . . . . . . . . . . . . . 77
Table 50. P5SMR Register (Group/Bank 0Fh, Register 5) . . . . . . . . . . . . . . . 77
Table 51. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 52. DC Characteristics for the Z86L97X (Mask Only) . . . . . . . . . . . . . . 80
Table 53. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

Architectural Overview

The Z86L972/Z86L973/Z86L974 family is designed to be used in a wide variety of
embedded control applications including home appliances, infrared (IR) remote
controls, security systems, and wireless keyboards.

It has three counter/timers, a general-purpose 8-bit counter/timer with a 6-bit pres-
caler and an 8-bit/16-bit counter/timer pair that can be used individually for gen-
eral-purpose timing or as a pair to automate the generation and reception of
complex pulses or signals. Unique features of the Z86L972/Z86L973/Z86L974
family of products include 489 bytes of general-purpose random-access memory
(RAM), 256 bytes of which are mapped into the program memory space and can
be used to store data variables or as executable RAM, a low-battery detection
flag, and a controlled current output pin, which is a regulated current source that
sinks a predefined current (I

CCO

). Table 1 highlights the basic product features of

these microcontrollers.

The Z8 microcontroller core offers more flexibility and performance than accumu-
lator-based microcontrollers. All 256 general-purpose registers, including dedi-
cated input/output (I/O) port registers, can be used as accumulators. This unique
register-to-register architecture avoids accumulator bottlenecks for high code effi-
ciency. The registers can be used as address pointers for indirect addressing, as
index registers, or for implementing an on-chip stack.

The Z8 has a sophisticated interrupt structure and automatically saves the pro-
gram counter and status flags on the stack for fast context-switching. Speed of
execution and smooth programming are also supported by a "working register
area" with short 4-bit register addresses.

The Z8 instruction set, consisting of 43 basic instructions, is optimized for high-
code density and reduced execution time. It is similar in form to the ZiLOG Z80
instruction set. The eight instruction types and six addressing modes together with
the ability to operate on bits, 4-bit nibbles or binary coded decimal (BCD) digits, 8-
bit bytes, and 16-bit words, make for a code-efficient, flexible microcontroller.

Table 1. Z86L972/Z86L973/Z86L94 Comparison

ROM

Z86L972

Z86L973

Z86L974

16K

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

Features

Two independent analog comparators

Controlled current output

489 bytes of RAM
233 bytes of general-purpose register-based RAM
256 bytes of RAM mapped into the program memory space that can be

used as data RAM or executable RAM

4K/8K/16K bytes of ROM

Counter/Timers

Special architecture to automate generation and reception of complex pulses
or signals:
Programmable 8-bit counter/timer (T8) with two 8-bit capture registers and

two 8-bit load registers

Programmable 16-bit counter/timer (T16) with one 16-bit capture register

pair and one 16-bit load register pair

Programmable input glitch filter for pulse reception

One general-purpose 8-bit counter/timer (T1) with 6-bit prescaler

Input/Output and Interrupts

Thirty-two I/Os, twenty-nine of which are bidirectional I/Os with programmable
resistive pull-up transistors (24 I/Os are available in the 28-pin configuration)

Sixteen I/Os are selectable as stop-mode recovery sources

Six interrupt vectors with nine interrupt sources
Three external sources
Two comparator interrupts
Three timer interrupts
One low-battery detector flag

Operating Characteristics

8-MHz operation

2.3 V to 5.5 V operating voltage

Low power consumption with three standby modes:
Stop

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

Halt
Low Voltage Standby

Low-battery detection flag

Low-voltage protection circuit (also known as V

, or voltage brownout,

circuit)

Watch-dog timer and power-on reset circuits

User-Programmable Option Bits

Clock source--RC/other (LC, resonator, or crystal)

Watch-dog timer permanently enable

32-kHz crystal

Port 2027 pull-up resistive transistor

Port 4042 pull-up resistive transistor

Port 4447 pull-up resistive transistor

Port 5051 pull-up resistive transistor

Port 5457 pull-up resistive transistor

Port 6063 pull-up resistive transistor

Port 6467 pull-up resistive transistor

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

Functional Block Diagram

Figure 1 shows the functional block diagram for the microcontrollers.

Figure 1. Functional Block Diagram

256 x 8-bit

Z8 Core

DD_padring

Program

Memory

256 Bytes

Two Analog

Comparators

16-Bit C/T

(Modulation)

Port 2

Port 6

Port 5

Port 4

Power Filter

Expanded

8-Bit C/T

(General)

8-Bit C/T

(Carrier)

Machine

Timing

and

Instruction

Control

XTAL 1
XTAL 2

*Controlled Current Output

Controlled

Current

Output

P43

P53

CREF2

CREF1

P50

P52

CIN2

CIN1

P51

Program memory is as follows:

Z86L972

4K ROM

Z86L973

8K ROM

Z86L974

16K ROM

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

Pin Descriptions

Figure 2 and Figure 3 show the pin names and locations.

Figure 2. 48-Pin SSOP Pin Assignments

P62
P63
P25
P26
P27

P44
P45
P46
P47

DD_padring

XTAL2
XTAL1

P51
P52
P53
P54
P64

P61
P60
P24
P23
P22
NC
NC
P21
P20
P43
VSS
VSS
P42
P41
P40
P50
P56
NC
NC
P57
P55
P67
P66
P65

Z86L972/
Z86L973/

Z86L974

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

21
22
23

46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
281
27
26

Notes:

1. All V

pins must be connected to ground.

2. All V

pins must be connected to the same filtering capacitor.

3. NC is no connection to the die.

4. Power must be connected to V

DD_padring

. Current passes to V

through the

internal power filter.

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

Figure 3. 40-Pin DIP Pin Assignment

P62
P63
P25
P26
P27

P44
P45
P46
P47

DD_padring

XTAL2
XTAL1

P51/CIN1/Captive Timer Input

P52/CIN2/T1 Timer Input (TIN)

P53/CREF2

P54/COUT1

P61
P60
P24
P23
P22
P21
P20
P43/Combined T8 T16 Output

P42
P41/T16 Output
P40/T8 Output
P50/CREF1
P56/T1 Timer Output
P57
P55/COUT2
P67
P66
P65
P64

Z86L972/
Z86L973/

Z86L974

2
3
4

5
6

7
8
9

10
11

12
13

14
15

18
19

39
38

37
36

35
34

31
30

29
28

27
26

25
24

23
22

Notes:

1. All V

pins must be connected to ground.

2. All V

pins must be connected to the same filtering capacitor.

3. Power must be connected to V

DD_padring

. Current passes to V

through the

internal power filter.

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

Pins Configuration

Table 2 describes the pins.

Table 2. Pin Descriptions

Pin #

Symbol

40
PDIP

48
SSOP Direction Description

P20

I/O

Port 2 Bit 0

P21

I/O

Port 2 Bit 1

P22

I/O

Port 2 Bit 2

P23

I/O

Port 2 Bit 3

P24

I/O

Port 2 Bit 4

P25

I/O

Port 2 Bit 5

P26

I/O

Port 2 Bit 6

P27

I/O

Port 2 Bit 7

P40

I/O

Port 4 Bit 0, T8 Output

P41

I/O

Port 4 Bit 1, T16 Output

P42

I/O

Port 4 Bit 2

P43

Output

T8/T16 Output, Controlled current output

P44

I/O

Port 4 Bit 4

P45

I/O

Port 4 Bit 5

P46

I/O

Port 4 Bit 6

P47

I/O

Port 4 Bit 7

P50, CREF1 28

I/O

Port 5 Bit 0, Comparator 1 reference

P51, CIN1

I/O

Port 5 Bit 1, Capture timer input, IRQ

P52, CIN2

Input

Port 5 Bit 2, Timer 1 timer input, IRQ

P53, CREF2 19

Input

Port 5 Bit 3, Comparator 2 reference, IRQ

P54

I/O

Port 5 Bit 4, High drive output

P55

I/O

Port 5 Bit 5, High drive output

P56

I/O

Port 5 Bit 6, Timer 1 output, High drive output

P57

I/O

Port 5 Bit 7, High drive output

P60

I/O

Port 6 Bit 0

P61

I/O

Port 6 Bit 1

P62

I/O

Port 6 Bit 2

P63

I/O

Port 6 Bit 3

P64

I/O

Port 6 Bit 4

P65

I/O

Port 6 Bit 5

P66

I/O

Port 6 Bit 6

P67

I/O

Port 6 Bit 7

XTAL1

Input

Crystal, Oscillator clock

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Operational Description

Central Processing Unit (CPU) Description

The Z8 architecture is characterized by a flexible I/O scheme, an efficient register
and address space structure and a number of ancillary features for cost-sensitive,
high-volume embedded control applications. ROM-based products are geared for
high-volume production (where the software is stable) and one-time programma-
ble equivalents for prototyping as well as volume production where time to market
or code flexibility is critical.

Architecture Type

The Z8 register-oriented architecture centers around an internal register file com-
posed of 256 consecutive bytes, known as the standard register file. The standard
register file consists of 4 I/O port registers (R2, R4, R5, and R6), 12 control and
status registers, 233 general-purpose registers, and 7 registers reserved for future
expansion. In addition to the standard register file, the Z86L972/Z86L973/
Z86L974 family uses 21 control and status registers located in the Z8 expanded
register file. Any general-purpose register can be used as an accumulator and
address pointer or an index, data, or stack register.

All active registers can be referenced or modified by any instruction that accesses
an 8-bit register, without the requirement for special instructions. Registers
accessed as 16 bits are treated as even-odd register pairs. In this case, the data's
most significant byte (MSB) is stored in the even-numbered register, while the
least significant byte (LSB) goes into the next higher odd-numbered register.

The Z8 CPU has an instruction set designed for the large register file. The instruc-
tion set provides a full compliment of 8-bit arithmetic and logical operations. BCD
operations are supported using a decimal adjustment of binary values, and 16-bit
quantities for addresses and counters can be incremented and decremented. Bit
manipulation and Rotate and Shift instructions complete the data-manipulation

XTAL2

Output

Crystal, Oscillator clock

12, 13 13, 14,

Z8 core power supply

DD_padring

Power supply (pad ring)

6, 7,
32

7, 8,
37, 38

Ground

Table 2. Pin Descriptions (Continued)

Pin #

Symbol

40
PDIP

48
SSOP Direction Description

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capabilities of the Z8 CPU. No special I/O instructions are necessary because the
I/O is mapped into the register file.

CPU Control Registers

The standard Z8 control registers govern the operation of the CPU. Any instruc-
tion which references the register file can access these control registers. The fol-
lowing are available control registers:

Stack Pointer (SP)

Program Control Flags (FLAGS)

Interrupt Control (IPR, IMR, and IRQ)

Stop Mode Recovery (SMR, P2SMR, and P5SMR)

Low-Battery Detect (LB) Flag

The Z8 uses a 16-bit Program Counter (PC) to determine the sequence of current
program instructions. The PC is not an addressable register.

Peripheral registers are used to transfer data, configure the operating mode, and
control the operation of the on-chip peripherals. Any instruction that references
the register file can access the peripheral registers. The following are peripheral
control registers:

T1 Timer/Counter (TMR, T1, and PRE1)

T8 Timer/Counter (CTR0, HI8, LO8, TC8H, and TC8L)

T16 Timer/Counter (CTR2, HI16, LO16, TC16H, and TC16L)

T8/T16 Control Registers (CTR1 and CTR3)

In addition, the four port registers are considered to be peripheral registers. The
following are port control registers:

Port Configuration Registers (P456CON and P3M)

Port 2 Control and Mode Registers (P2 and P2M)

Port 4 Control and Mode Registers (P4 and P4M)

Port 5 Control and Mode Registers (P5 and P5M)

Port 6 Control and Mode Registers (P6 and P6M)

The functions and applications of the control and peripheral registers are
explained in "Control and Status Registers" on page 47.

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Memory (ROM and RAM)

There are four basic address spaces available to support a wide range of configu-
rations:

Program memory (on-chip)

Standard register file

Expanded register file

Executable RAM

The Z8 standard register file totals up to 256 consecutive bytes organized as 16
groups of 16 eight-bit registers. These registers consist of I/O port registers,
general-purpose RAM registers, and control and status registers. Every RAM reg-
ister acts like an accumulator, speeding instruction execution and maximizing cod-
ing efficiency. Working register groups allow fast context switching.

The standard register file of the Z8 (known as Bank 0) has been expanded to form
16 expanded register file (ERF) banks. The expanded register file allows for addi-
tional system control registers and for the mapping of additional peripheral
devices into the register area. Each ERF bank can potentially consist of up to 256
registers (the same amount as in the standard register file) that can then be
divided into 16 working register groups. Currently, only Group 0 of ERF Banks F
and D (

0Fh

and

0Dh

) has been implemented.

In addition to the standard program memory and the RAM register files, the
Z86L972/Z86L973/Z86L974 family also has 256 bytes of executable RAM that
has been mapped into the upper 256 bytes of the program memory address
space (

FF00h

FFFFh

). Data can be written to the executable RAM by using the

LDC instruction.

Program Memory Structure

The first 12 bytes of program memory are reserved for the interrupt vectors.
These locations contain six 16-bit vectors that correspond to the six available
interrupts (IRQ

through IRQ

.) Address 12 (

0Ch

) up consists of on-chip read-only

memory (ROM).

After any reset operation (power-on reset, watch-dog timer time out, and stop
mode recovery), program execution resumes with the initial instruction fetch from
location

000Ch

. After a reset, the first routine executed must be one that initializes

the control registers to the required system configuration.

A unique feature of the Z86L972/Z86L973/Z86L974 family is the presence of 256
bytes of on-chip executable RAM. This random-access memory is in addition to
the standard Z8 register file memory available on all Z8 microcontrollers. As illus-
trated in Figure 4, the executable RAM is mapped into the upper 256 bytes of the

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64K program memory address space (

FF00h

FFFFh

). Data can be written to the

executable RAM by using the LDC instruction.

Memory locations between

8000h

and

FEFFh

have not been implemented on this

microcontroller.

The Z86L972/Z86L973/Z86L974 family does not have the capability of accessing
external memory.

Z8 Standard Register File (Bank 0)

Bank 0 of the Z8 expanded register file architecture is known as the standard reg-
ister file of the Z8. As shown in Figure 5, the Z8 standard register file consists of
16 groups of sixteen 8-bit registers known as Working Register (WR) groups.
Working Register Group F contains various control and status registers. The lower
half of Working Register Group 0 consists of I/O port registers (R0 to R7), the
upper eight registers are available for use as general-purpose RAM registers.

Location (Hex)
FFFF

256 bytes

Executable RAM

FF00

Not Implemented

3FFF (Z86L974)
1FFF (Z86L973)

PROGRAM

FFF (Z86L972)

MEMORY

000C

Location of the first byte of the initial instruction executed after

RESET

000B

IRQ

(lower byte)

000A

IRQ

(upper byte)

0009

IRQ

(lower byte)

0008

IRQ

(upper byte)

0007

IRQ

(lower byte)

0006

IRQ

(upper byte)

0005

IRQ

(lower byte)

0004

IRQ

(upper byte)

0003

IRQ

(lower byte)

0002

IRQ

(upper byte)

0001

IRQ

(lower byte)

0000

IRQ

(upper byte)

Figure 4. Program Memory Map

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Working Register Group 1 through Group E of the standard register file are avail-
able to be used as general-purpose RAM registers. You can use 233 bytes of gen-
eral-purpose RAM registers in the standard Z8 register file (Bank 0).

Figure 5. Standard Z8 Register File (Working Reg. Groups 0F, Bank 0)

Z8 Expanded Register File

In addition to the Standard Z8 Register File (Bank 0), Expanded Register File
Banks F and D of Working Register Group 0 have been implemented on the
Z86L972/Z86L973/Z86L974. Figure 6 illustrates the Z8 Expanded Register File
architecture. These two expanded register file banks of Working Register Group 0
provide a total of 32 additional RAM control and status registers. The Z86L972/
Z86L973/Z86L974 family has implemented 21 of the 32 available registers.

Grp/Bnk

Reg

Working Register Group Function

(

F0h

)

r0 to 15 Control and Status Registers

(

E0h

)

r0 to 15 General-purpose RAM registers

(

D0h

)

r0 to 15 General-purpose RAM registers

(

C0h

)

r0 to 15 General-purpose RAM registers

(

B0h

)

r0 to 15 General-purpose RAM registers

(

A0h

)

r0 to 15 General-purpose RAM registers

(

90h

)

r0 to 15 General-purpose RAM registers

(

80h

)

r0 to 15 General-purpose RAM registers

(

70h

)

r0 to 15 General-purpose RAM registers

(

60h

)

r0 to 15 General-purpose RAM registers

(

50h

)

r0 to 15 General-purpose RAM registers

(

40h

)

r0 to 15 General-purpose RAM registers

(

30h

)

r0 to 15 General-purpose RAM registers

(

20h

)

r0 to 15 General-purpose RAM registers

(

10h

)

r0 to 15 General-purpose RAM registers
r8 to 15 General-purpose RAM registers

(

00h

)

r0 to 7

I/O Port Registers

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Figure 6. Z8 Expanded Register File Architecture

Clock Circuit Description

The Z8 derives its timing from on-board clock circuitry connected to pins XTAL1
and XTAL2. The clock circuitry consists of an oscillator, a divide-by-two shaping
circuit, and a clock buffer. The oscillator's input is XTAL1, and the oscillator's out-
put is XTAL2. The clock can be driven by a crystal, a ceramic resonator, LC clock,
RC, or an external clock source.

Clock Control

The Z8 offers software control of the internal system clock using programming
register bits in the SMR register. This register selects the clock divide value and
determines the mode of STOP Mode Recovery.

The default setting is external clock divide-by-two. When bits 1 and 0 of the SMR
register are set to 0, the System Clock (SCLK) and Timer Clock (TCLK) are equal
to the external clock frequency divided by two.

When bit 1 of the SMR register is set to 1, then SCLK and TCLK equal the exter-
nal clock frequency. Refer to Table 51 on page 78 for the maximum clock fre-
quency.

A divide-by-16 prescaler of SCLK and TCLK allows you to selectively reduce
device power consumption during normal processor execution (under SCLK con-
trol) and/or HALT mode, where TCLK sources counter/timers and interrupt logic.
Combining the divide-by-2 circuitry with the divide-by-16 prescaler allows the
external clock to be divided by 32.

Z8 Standard Register File

F
E

D
C
B
A

9
8
7
6
5
4
3
2
1
0

Bank 0

Control and Status Reg.

I/O Port Registers

Working
Register
Groups

Banks 2 through C are
Reserved--Not Implemented

Group 0, Bank D

Group 0, Bank F

(Bank E is also reserved)

General-Purpose
RAM Registers

Z8 Expanded Register Files

Timer
Control
Registers

Stop Mode
Recovery and
Port Mode

Bank F

Registers

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Interrupts

The Z86L972/Z86L973/Z86L974 family allows up to six different interrupts, three
external and three internal, from nine possible sources. The six interrupts are
assigned as follows:

Three edge triggered external interrupts (P51, P52, and P53), two of which are
shared with the two analog comparators

One internal interrupt assigned to the T8 Timer

One internal interrupt assigned to the T16 Timer

One internal interrupt shared between the Low-Battery Detect flag and the T1
Timer

Table 3 presents the interrupt types, the interrupt sources, and the location of the
specific interrupt vectors.

These interrupts can be masked and their priorities set by using the Interrupt
Mask Register (IMR) and Interrupt Priority Register (IPR) (Figure 7.) When more
than one interrupt is pending, priorities are resolved by a priority encoder, con-
trolled by the IPR.

Table 3. Interrupt Types, Sources, and Vectors

Name

Source

Vector
Location Comments

IRQ

P52 (F/R), Comparator 2

0,1

External interrupt (P52) is triggered by
either rising or falling edge; internal
interrupt generated by Comparator 2
is mapped into IRQ

IRQ

P53 (F)

2,3

External interrupt (P53) is triggered by
a falling edge

IRQ

P51 (R/F), Comparator 1

4,5

External interrupt (P51) is triggered by
either a rising or falling edge; internal
interrupt generated by Comparator 1
is mapped into IRQ

IRQ

T16 Timer

6,7

Internal interrupt

IRQ

T8 Timer

8,9

Internal interrupt

IRQ

LVD, T1 Timer

10,11

Internal interrupt, LVD flag is
multiplexed with T1 Timer End-of-
Count interrupt

Notes:

F = Falling-edge triggered; R = Rising-edge triggered.
When LVD is enabled, IRQ5 is triggered only by low-voltage detection. Timer
1 does not generate an interrupt.

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Figure 7. Interrupt Block Diagram

Interrupt requests are stored in the Interrupt Request Register (IRQ), which can
also be used for polling. When an interrupt request is granted, the Z8 enters an
"interrupt machine cycle" that globally disables all other interrupts, saves the pro-
gram counter (the address of the next instruction to be executed) and status flags,
and finally branches to the vector location for the interrupt granted. It is only at this
point that control passes to the interrupt service routine for the specific interrupt.

All six interrupts can be globally disabled by resetting the master Interrupt Enable
(bit 7 of the IMR) with a Disable Interrupts (DI) instruction. Interrupts are globally
enabled by setting the same bit with an Enable Interrupts (EI) instruction.

Descriptions of three interrupt control registers--the Interrupt Request Register,
the Interrupt Mask Register, and the Interrupt Priority Register--are provided in
"Register Summary" on page 47. The Z8 family supports both vectored and polled
interrupt handling.

External Interrupt Sources

External sources involve interrupt request lines P51, P52, and P53 (IRQ

, IRQ

and IRQ

, respectively.) IRQ

, IRQ

, and IRQ

are generated by a transition on

the corresponding port pin. As shown in Figure 8, when the appropriate port pin
(P51, P52, or P53) transitions, the first flip-flop is set. The next two flip-flops syn-
chronize the request to the internal clock and delay it by two internal clock peri-
ods. The output of the most recent flip-flop (IRQ

, IRQ

, or IRQ

) sets the

corresponding Interrupt Request Register bit.

EI Instruction

Power-On Reset (POR)

Interrupt Request Register

(IRQ,FAH)

Reset

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Figure 8. External Interrupt Sources IRQ

IRQ

Block Diagram

The programming bits for the Interrupt Edge Select function are located in the IRQ
register, bits 6 and 7. The configuration of these bits and the resulting interrupt
edge is shown in Table 4.

Although interrupts are edge triggered, minimum interrupt
request Low and High times must be observed for proper
operation. See "Electrical Characteristics" on page 78 for exact
timing requirements (T

IL, T

IH) on external interrupt

requests.

Internal Interrupt Sources

Internal sources are ORed with the external sources, so that either an internal or
external source can trigger the interrupt.

Interrupt Request Register Logic and Timing

Figure 9 shows the logic diagram for the Interrupt Request Register. The leading
edge of an interrupt request sets the first flip-flop. It remains set until the interrupt
requests are sampled.

Table 4. Interrupt Edge Select for External Interrupts

Interrupt Request Register

Interrupt Edge

Bit 7

Bit 6

IRQ

(P51)

IRQ

(P52)

Falling

Rising

Falling

Rising/Falling

Note:

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Figure 9. IRQ Logic

Internal interrupt requests are sampled during the most recent clock cycle before
an Op Code fetch (see Figure 10.) External interrupt requests are sampled two
internal clocks earlier than internal interrupt requests because of the synchroniz-
ing flip-flops shown in Figure 8.

Figure 10. Interrupt Request Timing

At sample time, the interrupt request is transferred to the second flip-flop shown in
Figure 9, which drives the interrupt mask and priority logic. When an interrupt
cycle occurs, this flip-flop is reset only for the highest priority level that is enabled.

You have direct access to the second flip-flop by reading and writing to the IRQ.
The IRQ is read by specifying it as the source register of an instruction, and the
IRQ is written by specifying it as the destination register.

Interrupt Initialization

After RESET, all interrupts are disabled and must be re-initialized before vectored
or polled interrupt processing can begin. The Interrupt Priority Register, Interrupt
Mask Register, and Interrupt Request Register must be initialized, in that order, to

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start the interrupt process. However, the IPR does not have to be initialized for
polled processing.

Interrupts must be globally enabled using the EI instruction. Setting bit 7 of the
IMR is not sufficient. Subsequent to this EI instruction, interrupts can be enabled
either by IMR manipulation or by use of the EI instruction, with equivalent effects.

Additionally, interrupts must be disabled by executing a DI instruction before the
IPRs or IMRs can be modified. Interrupts can then be enabled by executing an EI
instruction.

IRQ Software Interrupt Generation

IRQ can be used to generate software interrupts by specifying IRQ as the destina-
tion of any instruction referencing the Z8 Standard Register File. These Software
Interrupts (SWIs) are controlled in the same manner as hardware-generated
requests (in other words, the IPR and the IMR control the priority and enabling of
each SWI level).

To generate a SWI, the request bit in the IRQ is set as follows:

IRQ,

NUMBER

where the immediate data, NUMBER, has a 1 in the bit position corresponding to
the appropriate level of the SWI.

For example, for an SWI on IRQ5, NUMBER would have a 1 in bit 5. With this
instruction, if the interrupt system is globally enabled, IRQ5 is enabled, and there
are no higher priority pending requests, control is transferred to the service routine
pointed to by the IRQ5 vector.

Reset Conditions

A system reset overrides all other operating conditions and puts the Z8 into a
known state. The control and status registers are reset to their default conditions
after a power-on reset (POR) or a Watch-Dog Timer (WDT) time-out while in RUN
mode. The control and status registers are not reset to their default conditions
after Stop Mode Recovery (SMR) while in HALT or STOP mode.

General-purpose registers are undefined after the device is powered up. Reset-
ting the Z8 does not affect the contents of the general-purpose registers. The reg-
isters keep their most recent value after any reset, as long as the reset occurs in
the specified V

operating range. Registers do not keep their most recent state

from a V

reset, if V

drops below V

RAM

(see Table 51 on page 78).

Following a reset (see Table 5), the first routine executed must be one that initial-
izes the control registers to the required system configuration.

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Table 5. Control and Status Register Reset Conditions

Address

Reset Value

Register Function

Grp/Bnk Register

Symbol

R/W 7

F0h

r13 (R253)

R/W 0

Stack Pointer

F0h

r15 (R255)

R/W X

Program Control Flags

F0h

r12 (R252)

Flags

R/W X

Low Battery Detect

0Dh

r12

R/W 1

Interrupt Mask

F0h

r11 (R251)

IMR

R/W 0

Interrupt Priority

F0h

r9 (R249)

IPR

Interrupt Request

F0h

r10 (R250)

IRQ

R/W 0

Port Configuration (A)

0Fh

P456CON

R/W 0

Port Configuration (B)

F0h

r7 (R247)

P3M

Port 2 Data

00h

r2 (R2)

R/W X

Port 2 Mode

F0h

r6 (R246)

P2M

Port 4 Data

00h

r4 (R4)

R/W X

Port 4 Mode

0Fh

P4M

R/W 1

1** 1

Port 5 Data

00h

r5 (R5)

R/W X

Port 5 Mode

0Fh

P5M

R/W 1

Port 6 Data

00h

r6 (R6)

R/W X

Port 6 Mode

0Fh

P6M

R/W 1

T1 Timer Data

F0h

r2 (R242)

R/W 0

T1 Timer Mode

F0h

r1 (R241)

TMR

R/W 0

T1 Timer Prescale

F0h

r3 (R243)

PRE1

R/W 0

T8/T16 Control (A)

0Dh

CTR1

R/W 0

0* 0* 0

T8/T16 Control (B)

0Dh

CTR3

R/W 0

0* X

T8 Timer Control

0Dh

CTR0

R/W 0

0* 0* 0* 0* 0* 0

T8 High Capture

0Dh

r11

HI8

T8 Low Capture

0Dh

r10

LO8

R/W 0

T8 High Load

0Dh

TC8H

R/W 0

T8 Low Load

0Dh

TC8L

R/W 0

T16 Timer Control

0Dh

CTR2

R/W 0

T16 High Capture

0Dh

HI16

R/W 0

T16 Low Capture

0Dh

LO16

R/W 0

T16 High Load

0Dh

TC16H

R/W 0

T16 Low Load

0Dh

TC16L

R/W 0

Stop Mode Recovery

0Fh

r11

SMR

R/W 0

Port 2 SMR Source

0Fh

P2SMR

R/W 0

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Power-On Reset

A POR (cold start) always resets the Z8 control and status registers to their default
conditions. A POR sets bit 7 of the Stop Mode Recovery register to 0 to indicate
that a cold start has occurred.

A timer circuit clocked by a dedicated on-board RC oscillator is used for the
Power-On Reset Timer (TPOR) function. The POR time is specified as T

POR

time allows V

and the oscillator circuit to stabilize before instruction exe-

cution begins.

The POR delay timer circuit is a one-shot timer triggered by one of three condi-
tions:

Power Fail to Power OK status including recovery from Low Voltage (V

LV)

Standby mode

STOP-Mode Recovery (when bit 5 of the SMR register = 1)

WDT time-out

Under normal operating conditions, a stop mode recovery event always triggers
the POR delay timer. This delay is necessary to allow the external oscillator time
to stabilize. When using an RC or LC oscillator (with a low Q factor), the shorter
wake-up time means the delay can be eliminated.

Bit 5 of the SMR register selects whether the POR timer delay is used after Stop-
Mode Recovery or is bypassed. If bit 5 =1, then the POR timer delay is used. If bit
5 = 0, then the POR timer delay is bypassed. In this case, the SMR source must
be held in the recovery state for 5 TpC to pass the Reset signal internally.

Watch-Dog Timer (WDT)

The WDT is a retriggerable one-shot timer that resets the Z8 if it reaches its
terminal count. When operating in the RUN modes, a WDT reset is functionally
equivalent to a hardware POR reset. If the mask option of the permanently
enabled watch-dog timer is selected, it runs when power up. If the option is not

Port 5 SMR Source

0Fh

P5SMR

R/W 0

Notes:

This register is not reset following Stop Mode Recovery (SMR).

*This bit is not reset following SMR.
X means this bit is undefined at POR and is not reset following SMR.
**In OTP, the default for P43 is open-drain output at power up; you need to
initialize the P43 data. In the mask part, the P43 output is disabled until it is
configured as output.

Table 5. Control and Status Register Reset Conditions (Continued)

Address

Reset Value

Register Function

Grp/Bnk Register

Symbol

R/W 7

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selected, the WDT is initially enabled by executing the WDT instruction and
refreshed on subsequent executions of the WDT instruction.

The WDT instruction does not affect the Zero (Z), Sign (S), and Overflow (V) flags.
Permanently enabled WDTs are always enabled, and the WDT instruction is used
to refresh it. The WDT cannot be disabled after it has been initially enabled. The
WDT is off during both HALT and STOP modes.

The WDT circuit is driven by an on-board RC oscillator. The time-out period for the
WDT is fixed to a typical value (see Table 53 on page 81).

Power Management

In addition to the standard RUN mode, the Z8 supports three power-down modes
to minimize device current consumption. The following three modes are sup-
ported:

HALT

STOP

Low-Voltage Standby

Table 6 shows the status of the internal CPU clock (SCLK), the internal Timer
clock (TCLK), the external oscillator, and the Watch-Dog Timer during the RUN
mode and three low-power modes.

Using the Power-Down Modes

In order to enter HALT or STOP mode, it is necessary to first flush the instruction
pipeline to avoid suspending execution in mid-instruction. You can flush the
instruction pipeline by executing a NOP (Op Code =

FFh

) immediately before the

appropriate sleep instruction. For example:

Table 6. Clock Status in Operating Modes

Operating Mode

SCLK TCLK External OSC WDT*

RUN

HALT Off

Off

STOP

Off

Low-Voltage Standby

Off

Note: * When WDT is enabled by the mask option bit

Mnemonic Comment

Op Code

NOP

; clear the pipeline

FFh

STOP

; enter STOP mode

6Fh

Z86L972/Z86L973/Z86L974

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P R E L I M I N A R Y

HALT

HALT mode suspends instruction execution and turns off the internal CPU clock
(SCLK). The on-chip oscillator circuit remains active, so the internal Timer clock
(TCLK) continues to run and is applied to the counter/timers and interrupt logic.

An interrupt request, either internally or externally generated, must be executed
(enabled) to exit HALT mode. After the interrupt service routine, the program con-
tinues from the instruction immediately following the HALT.

The HALT mode can also be exited by a POR. In this case, the program execution
restarts at the reset address

000Ch

STOP

STOP mode provides the lowest possible device standby current. This instruction
turns off both the internal CPU clock (SCLK) and internal Timer clock (TCLK) and
reduces the standby current to the minimum.

The STOP mode is terminated by a POR or SMR source. Terminating the STOP
mode causes the processor to restart the application program at address

000Ch

When the STOP instruction is executed, the microcontroller goes into the
STOP mode despite any state/change of the state of the port. The ports
need to be checked immediately before the NOP and STOP instructions to
ensure the right input logic before waiting for the change of the ports.

Stop Mode Recovery Sources

Exiting STOP mode using an SMR source is greatly simplified in the Z86L972/
Z86L973/Z86L974 family. The Z86L972/Z86L973/Z86L974 family of products
allows 16 individual I/O pins (Ports 2 and 5) to be used as stop-mode recovery
sources. The STOP mode is exited when one of these SMR sources is toggled. A
transition from either low to high or high to low on any pin of Port 2 or Port 5 if the
pin is identified as an SMR source will effect an SMR.

There are three registers that control STOP mode recovery:

Stop Mode Recovery

Port 2 Stop Mode Recovery (P2SMR)

Port 5 Stop Mode Recovery (P5SMR)

Mnemonic Comment

Op Code

NOP

; clear the pipeline

FFh

HALT

; enter HALT mode

7Fh

Note:

Z86L972/Z86L973/Z86L974

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P R E L I M I N A R Y

The functions and applications of these registers are explained in "Stop-Mode
Recovery Control Registers" on page 75.

Low-Voltage Standby

An on-chip voltage comparator checks that the V

level is at the required level

for correct operation of the Z8. When V

falls below the low-voltage trip voltage

), reset is globally driven, and then the device is put in a low-current standby

mode with the external oscillator stopped. If the V

remains above V

RAM

, the

RAM content is preserved.

When the power level rises above the V

level, the device performs a POR and

functions normally.

The minimum operating voltage varies with temperature and operating frequency,
while V

varies with temperature only.

I/O Ports

The Z86L972/Z86L973/Z86L974 family has up to 32 lines dedicated to input and
output in the 40-pin configuration. These lines are grouped into four 8-bit ports
known as Port 2, Port 4, Port 5, and Port 6. All four ports are bit programmable as
either inputs or outputs with the exception of P52, P53, and P43. P52 and P53 are
input only as they are used in factory programming. P43 is the controlled current
output and is therefore output only.

All ports have push-pull CMOS outputs. In addition, the push-pull outputs can be
turned off for open-drain operation using the P456CON register.

Internal resistive pull-up transistors are available as a user-defined mask option
on all ports. For Ports 4, 5, and 6, the pull-ups are nibble selectable. For Port 2,
the pull-up option applies to all eight I/O lines.

Internal pull-ups are disabled on any given pin or group of port
pins when those pins are programmed as outputs.

Mode Registers

Each port has an associated Mode Register that determines the port's functions
and allows dynamic change in port functions during program execution. Port and
Mode Registers are mapped into the Standard Register File. Because of their
close association, Port and Mode Registers are treated like any other
general-purpose register. There are no special instructions for port manipulation.
Any instruction that addresses a register can address the ports. Data can be
directly accessed in the Port Register, with no extra moves.

Note:

Z86L972/Z86L973/Z86L974

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P R E L I M I N A R Y

Input and Output Registers

Each of the four ports (Ports 2, 4, 5, and 6) has an input register, an output regis-
ter, and associated buffer and control logic. Because there are separate input and
output registers associated with each port, writing bits defined as inputs store the
data in the output register. This data cannot be read as long as the bits are defined
as inputs. However, if the bits are reconfigured as output, the data stored in the
output register is reflected on the output pins and can then be read. This mecha-
nism allows you to initialize the outputs before driving their loads.

Because port inputs are asynchronous to the Z8 internal clock, a READ operation
could occur during an input transition. In this case, the logic level might be uncer-
tain (somewhere between a logic 1 and 0).

General Port I/O

The eight I/O lines of each port (except P43, P52, and P53) can be configured
under software control to be either input or output, independently. Bits pro-
grammed as outputs can be globally programmed as either push-pull or open-
drain. See Figure 11.

Figure 11. General Input/Output Pin

Read/Write Operations

The ports are accessed as general-purpose registers. Port registers are written by
specifying the port register as an instruction's destination register. Writing to a port
causes data to be stored in the output register of the port, and reflected externally
on any bit configured as an output.

Open-Drain

I/O

Mask

Option

Pad

Out

Pull-Up

Note: * Pull-up resistance is
about 200 K

at 2.3 V and

75 K

at 5.0 V with +50%

tolerance.

Z86L972/Z86L973/Z86L974

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P R E L I M I N A R Y

Ports are read by specifying the port register as the source register of an instruc-
tion. When an output bit is read, data on the external pin is returned. Under normal
loading conditions, returning data on the external pin is equivalent to reading the
output register. However, if a bit is defined as an open-drain output, the data
returned is the value forced on the output pin by the external system. This value
might not be the same as the data in the output register. Reading input bits also
returns data on the external pins.

Special Functions

Table 7 defines the special functions of Ports 4 and 5.

Peripherals

Analog Comparators

The Z86L972/Z86L973/Z86L974 family includes two independent on-chip gen-
eral-purpose analog comparators as shown in Figure 12. The comparators are
multiplexed with a digital input signal by the P456CON register. They can also be
used to generate interrupts IRQ0 and IRQ2. The comparators are turned off in
STOP mode.

Table 7. Special Port Pin Functions

Function

Pin

Signal

Configuration Register

Analog Comparator Inputs

P51

CIN1

P456CON

P52

CIN2

P456CON

Analog Comparator
References

P50

CREF1

P53

CREF2

Analog Comparator Outputs

P54

COUT1

P55

COUT2

External Interrupts

P52

IRQ

IMR and IRQ

P53

IRQ

IMR and IRQ

P51

IRQ

IMR and IRQ

External Clock Input

P52

TMR and PRE1

Capture Timer Input

P51

Demodulator_Input CTR1

T1 Timer Output

P56

T1OUT

TMR

T8 Output

P40

P40_Out

CTR0

T16 Output

P41

P41_Out

CTR2

Combined T8/T16 Output
Controlled Current Output

P43

P43_Out

CTR1

ZiLOG Test Mode

P41

DSn Enable

P456CON

P42

ASn Enable

P456CON

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Figure 12. Analog Comparators

Active Glitch Filter

The Z86L972/Z86L973/Z86L974 family incorporates an active power/glitch filter
that can be used to improve the quality of the power supply when the device is
operating in noisy environments. The chips use two separate power buses:

pad ring power bus (all the output drivers plus the crystal/RC oscillator) called
V

DD_padring

core power bus (all digital circuitry) called V

Depending on the pin availability, one or more of the power busses are connected
together.

The active power filter can be used in the packages that have the V

separate.

Figure 13 shows the internal schematic.

P51

Comparator 1

P50

P52

Comparator 2

P53

P456CON

IRQ2, P51 Data Latch

IRQ0, P52 Data Latch

(CIN1)

(CREF1)

(CIN2)

(CREF2)

Bit4 1 = comparator
0 = digital

Bit5 1 = comparator
0 = digital

Z86L972/Z86L973/Z86L974

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P R E L I M I N A R Y

Z86L972/Z86L973/Z86L974

Figure 13. Active Glitch/Power Filter

When the internal power/glitch filter is not used, both V

DD_padring

and V

must be

connected together externally to the power supply.

When the internal circuitry is used, the V

DD_padring

has to be connected to the

power supply and the V

has to be connected to an external energy storage

capacitor (1

-10 µ

F range). The core is connected only to this capacitor during

power supply glitches.

Table 8 describes the active glitch/filter specifications.

On the wafer level, all three power buses are available. Depending on the number
of pins of the package, one or more power buses are connected together.

The active glitch/power filter effectively increases the noise immunity for battery-
operated designs where the controller is driving high current loads (IR LED, key-
board scanning).

Table 8. Active Glitch/Filter Specifications (Preliminary)

Parameter

Max

Min

Condition

Diff. stage gain

75 dB

Diff. stage bandwidth

15 MHz

Rise time

255 ns

50 mV pulse

Fall time

214 ns

50 mV pulse

dson

DD_padring

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P R E L I M I N A R Y

Controlled Current Output

P43 is an open-drain pin that can be configured as output or Tristate High Imped-
ance. To function properly, Bit 3 of P4M must be set to zero to configure the pin as
an open-drain output. After reset, P43 defaults to Tristate High Impedance. The
data at Port 4 must be initialized as it is undefined at power-on reset.

The current output is a controlled current source that is controlled by the output of
the value of P43 (see Table 9). P43 cannot be configured as input, and if P43 is
read, P43 always returns the state of the output value (1 for no sink and 0 for
sink).

Before going into STOP mode, P43 must be set to 1 to reduce STOP mode cur-
rent.n

The pad driver can function in two modes:

controlled current output, when the voltage on the pad is over a minimum
value

resistive pull down when the driver cannot regulate the current; in this mode,
the gate of the NMOS pull down is raised to the power rail.

The I-V characteristics of the pad are presented in Figure 14.

Table 9. Current Sink Pad P43 Specifications (Preliminary)

Parameter

Min

Max

Conditions

Rise time

0.4

LED load

Fall time

0.02

LED load

outmin

0.54 V

@27C

Comparator response

0.2

Regulated current

80 mA

120 mA

Internal resistance

pad

outmin

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P R E L I M I N A R Y

Figure 14. I-V Characteristics for the Current Sink Pad P43

The CPU reads the mode of the pad driver by reading bit number 2 from the LB
register. This bit is the output of a Set-Reset flip-flop that sets whenever the volt-
age on the pad is lower than V

outmin

and is reset by a CPU write to the respective

T1 Timer

The Z86L972/Z86L973/Z86L974 family provides one general-purpose 8-bit
counter/timer, T

, driven by its own 6-bit prescaler, PRE

. The T

counter/timer is

independent of the processor instruction sequence, which relieves software from
time-critical operations such as interval timing and event counting.

The T

counter/timer operates in either single-pass or continuous mode. At the

end-of-count, counting either stops or the initial value is reloaded and counting
continues. Under software control, new values are loaded immediately or when
the end-of-count is reached. Software also controls the counting mode, how the
counter/timer is started or stopped, and the counter/timer's use of I/O lines. Both
the counter and prescaler registers can be altered while the counter/timer is run-
ning.

Z86L972/Z86L973/Z86L974

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P R E L I M I N A R Y

Counter/timer 1 is driven by a timer clock generated by dividing the internal clock
by four. The divide-by-four stage, the 6-bit prescaler, and the 8-bit counter/timer
form a synchronous 16-bit divide chain. Counter/timer T

can also be driven by an

external input (T

) using Port P52. Port P5

can serve as a timer output (T

OUT

)

through which T

or the internal clock can be output. The timer output toggles at

the end-of-count. Figure 15 is a block diagram of the counter/timer.

Figure 15. T

Counter/Timer Block Diagram

OSC

External Clock

Clock

Logic

Internal
Clock

8-Bit

Down Counter

6-Bit

Down Counter

Initial Value

PRE1

Initial Value

Current Value

Internal Data Bus

OUT

IRQ5

Internal Clock

Gated Clock

Triggered Clock

Write

Read

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

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P R E L I M I N A R Y

The counter/timer, prescaler, and associated mode registers are mapped into the
register file as shown in Figure 16. The software uses the counter/timer as a gen-
eral-purpose register, which eliminates the need for special instructions.

Figure 16. Register File

Prescaler and Counter/Timer

The prescaler PRE

(

F3h

) consists of an 8-bit register and a 6-bit down-counter as

shown in Figure 15 on page 30. The prescaler register is a read-write register.
Figure 17 shows the prescaler register.

R243 PRE1

Prescaler 1 Register

(

F3h

; Read/Write)

Figure 17. Prescaler 1 Register

DEC

Hex identifiers

243

T1 prescaler

F3 PRE1

242

Timer/counter 1

F2 T1

241

Timer mode

F1 TMR

Count mode
1 = T

modulo-N

0 = T

single pass

Clock source
1 = T

internal

0 = T

external (T

)

Prescaler modulo
(range: 164 decimal,

01h

00h

)

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P R E L I M I N A R Y

The six most significant bits (D

) of PRE

hold the prescaler count modulo, a

value from 11 to 64 decimal. The prescaler register also contains control bits that
specify T

counting modes. These bits also indicate whether the clock source for

is internal or external.

The counter/timer T

(

F2h

) consists of an 8-bit down-counter, a write-only register

that holds the initial count value, and a read-only register that holds the current
count value (see Figure 15 on page 30). The initial value can range from 1 to 256
decimal (

01h

02h

, ...,

00h

). Figure 18 illustrates the counter/timer register.

R242 T1

Counter/Timer 1 Register

(

F2h

; Read/Write)

Figure 18. Counter/Timer 1 Register

Counter/Timer Operation

Under software control, T

is started and stopped using the Timer Mode register

(

F1h

) bits D

: a Load bit and an Enable Count bit. See Figure 19.

R241 TMR

Timer Mode Register

(

F1h

; Read/Write)

Figure 19. Timer Mode Register

Initial value when written
(range 1256 decimal,

01h

00h

)

Current value when read

Reserved

0 = No function
1 = Load T

0 = Disable T

count

1 = Enable T

count

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

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P R E L I M I N A R Y

Load and Enable Count Bits

Setting the Load bit D

transfers the initial values in the prescaler and the

counter/timer registers into their respective down-counters. The next internal clock
resets bit D

, readying the Load bit for the next load operation. The initial val-

ues can be loaded into the down-counters at any time. If the counter/timer is run-
ning, the counter/timer continues to run and starts the count over with the initial
value. Therefore, the Load bit actually functions as a software re-trigger.

The T

counter/timer remains at rest as long as the Enable Count bit D

. To

enable counting, the Enable Count bit D

must be set to

. Counting actually starts

when the Enable Count bit is written by an instruction. The first decrement occurs
four internal clock periods after the Enable Count bit has been set.

The Load and Enable Count bits can be set at the same time. For example, using
the instruction

OR TMR #%0C

sets both D

and D

of TMR to

. The initial values of

PRE

and T

are loaded into their respective counters, and the count is started

after the M2T2 machine state after the operand is fetched as shown in Figure 20.

Figure 20. Starting the Count

Prescaler Operations

During counting, the programmed clock source drives the prescaler 6-bit counter.
The counter is counted down from the value specified by bits D

of the corre-

sponding prescaler register, PRE

or PRE

(Figure 21). When the prescaler

counter reaches its end-of-count, the initial value is reloaded and counting contin-
ues. The prescaler never actually reaches zero. For example, if the prescaler is
set to divide by three, the count sequence is as follows:

3-2-1-3-2-1-3-2...

#03 is fetched

TMR is written;

counter/timers

are loaded

first decrement

occurs four

clocks later

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

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P R E L I M I N A R Y

R243 PRE1

Prescaler 1 Register

(

F3h

; Read/Write)

Figure 21. Counting Modes

When the PRE

prescaler divides by 64. If that number is 000001, the prescaler does not divide
and passes its clock on to T

Each time the prescaler reaches its end-of-count, a carry is generated, which
allows the counter/timer to decrement by one on the next timer clock input. When
T

and PRE

both reach their end-of-count, an interrupt request is generated--

IRQ

for T

. Depending on the counting mode selected, the counter/timer either

comes to rest with its value at

00h

(single-pass mode), or the initial value is auto-

matically reloaded and counting continues (continuous mode). In single-pass
mode, the prescaler still continues to decrement when the timer T

has reached

its end-of-count. The prescaler always starts from its programmed value upon
restarting the counter.

The counting modes are controlled by bit D

of PRE

, with D

cleared to

for sin-

gle-pass counting mode or set to

for continuous mode.

The counter/timer can be stopped at any time by setting the Enable Count bit to

and restarted by setting the Enable Count bit back to

. The T

counter/timer con-

tinues its count value at the time it was stopped. The current value in the T

counter/timer can be read at any time without affecting the counting operation.

New initial values can be written to the prescaler or the counter/timer registers at
any time. These values are transferred to their respective down-counters on the
next load operation. If the counter/timer mode is continuous, the next load occurs
on the timer clock following an end-of-count. New initial values must be written
before the load operation because the prescaler always effectively operates in
continuous count mode.

If the value loaded in the T

01h

, the timer is actually not timing or

counting at all; the timer is passing the prescaler end-of-count through. Because
the prescaler is continuously running, regardless of the single-pass/continuous
mode operation, the 8-bit timer continuously times out at the rate of the prescaler
end-of-count if the T

timer value is programmed to

01h

Count mode
1 = T

modulo-N

0 = T

single pass

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

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P R E L I M I N A R Y

The time interval (i) until end-of-count, is given by

i = t x p x v

where t is 8 divided by XTAL frequency, p is the prescaler value (1 64), and v is
the counter/timer value (1 256). The prescaler and counter/timer are true divide-
by-n counters.

OUT

Modes

The Timer Mode register TMR (

F1h

) (Figure 22) is used in conjunction with the

Port 5 Mode register P5M to configure P5

for T

OUT

operation. In order for T

OUT

function, P5

must be defined as an output line by setting P5M bit D

. Output

is controlled by one of the counter/timers (T

or T

) or the internal clock.

R241 TMR

Timer Mode Register

(

F1h

; Read/Write)

Figure 22. Timer Mode Register T

OUT

Operation

The P5

output is selected by TMR bits D

and D

. T

is selected by setting D

and D

and

, respectively. The counter/timer T

OUT

mode is turned off by set-

ting TMR bits D

and D

both to

, freeing P3

to be a data output line.

OUT

is initialized to a logic 1 whenever the TMR Load bit D

is set to

At end-of-count, the interrupt request line IRQ

clocks a toggle flip-flop. The out-

put of this flip-flop drives the T

OUT

line P5

. In all cases, when the counter/timer

reaches its end-of-count, T

OUT

toggles to its opposite state (see Figure 23). If, for

example, the counter/timer is in continuous counting mode, T

OUT

has a 50% duty

cycle output. You can control the duty cycle by varying the initial values after each
end-of-count.

0 = No function
1 = Load T

OUT

modes

OUT

off = 00

Reserved = 01
T

out = 10

Internal clock out = 11

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

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P R E L I M I N A R Y

Figure 23. Counter/Timer Output Using T

OUT

The internal clock can be selected as output instead of T

by setting TMR bits D

and D

both to

. The internal clock (XTAL frequency/2) is then directly output on

(Figure 24).

Figure 24. Internal Clock Output Using T

OUT

While programmed as T

OUT

, P5

cannot be modified by a write to port register P5.

However, the Z8 software can examine P5

's current output by reading the port

Modes

The Timer Mode register TMR (

F1h

) (Figure 25) is used in conjunction with the

Prescaler register PRE

(

F3h

) (Figure 26) to configure P5

as T

. T

is used in

conjunction with T

in one of four modes:

External clock input

Gated internal clock

Triggered internal clock

Retriggerable internal clock

OUT

IRQ5 (T1 end-of-count)

OSC

Internal clock

OUT

TMR

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

R241 TMR

Timer Mode Register

(

F1h

; Read/Write)

Figure 25. Timer Mode Register T

Operation

R243 PRE1

Prescaler 1 Register

(

F3h

; Write Only)

Figure 26. Prescaler 1 T

Operation

The T

counter/timer clock source must be configured for external by setting

PRE

bit D

. The Timer Mode register bits D

and D

can then be used to

select the T

operation.

For T

to start counting as a result of a T

input, the Enable Count bit D

in TMR

must be set to

. When using T

as an external clock or a gate input, the initial

values must be loaded into the down-counters by setting the Load bit D

in TMR

before counting begins. Initial values are automatically loaded in Trigger and

Retrigger modes, so software loading is unnecessary.

Configure P5

as an input line by setting P5M bit D

modes

External clock input = 00
Gate input = 01
Trigger input = 10
(non-retriggerable)
Trigger input = 11
(retriggerable)

Clock source
1 = T

internal

0 = T

external (T

)

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

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P R E L I M I N A R Y

Each High-to-Low transition on T

generates interrupt request IRQ

, regardless

of the selected T

mode or the enabled/disabled state of T

. IRQ

must therefore

be masked or enabled according to the needs of the application.

External Clock Input Mode

The T

External Clock Input mode (TMR bits D

and D

both set to

) supports

the counting of external events, where an event is considered to be a High-to-Low
transition on T

(see Figure 27) occurrence (single-pass mode) or on every nth

occurrence (continuous mode) of that event.

Figure 27. External Clock Input Mode

Gated Internal Clock Mode

The T

Gated Internal Clock mode (TMR bits D

and D

set to

and

, respec-

tively) measures the duration of an external event. In this mode, the T

prescaler

is driven by the internal timer clock, gated by a High level on T

(see Figure 28).

counts while T

is High and stops counting when T

is Low. Interrupt request

IRQ

is generated on the High-to-Low transition of T

, signaling the end of the

gate input. Interrupt request IRQ

is generated if T

reaches its end-of-count.

Figure 28. Gated Clock Input Mode

Internal clock

IRQ5

clock

PRE1

IRQ0

TMR
D

= 00

Internal clock

IRQ5

gate

OSC

IRQ0

TMR
D

= 01

PRE1

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

Triggered Input Mode

The T

Triggered Input mode (TMR bits D

and D

set to

and

, respectively)

causes T

to start counting as the result of an external event (see Figure 29). T

then loaded and clocked by the internal timer clock following the first High-to-Low
transition on the T

input. Subsequent T

transitions do not affect T

. In the sin-

gle-pass mode, the Enable bit is reset whenever T

reaches its end-of-count. Fur-

ther T

transitions have no effect on T

until software sets the Enable Count bit

again. In continuous mode, when T

is triggered, counting continues until software

resets the Enable Count bit. Interrupt request IRQ

is generated when T

reaches

its end-of-count.

Figure 29. Triggered Clock Mode

Retriggerable Input Mode

The T

Retriggerable Input mode (TMR bits D

and D

both set to

) causes T

load and start counting on every occurrence of a High-to-Low transition on T

(see Figure 29). Interrupt request IRQ

is generated if the programmed time inter-

val (determined by T

prescaler and counter/timer register initial values) has

elapsed since the last High-to-Low transition on T

. In single-pass mode, the

end-of-count resets the Enable Count bit. Subsequent T

transitions do not

cause T

to load and start counting until software sets the Enable Count bit again.

In continuous mode, counting continues when T

is triggered until software resets

the Enable Count bit. When enabled, each High-to-Low T

transition causes T

Internal clock

IRQ5

trigger

OSC

IRQ0

TMR
D

= 11

PRE1

Edge
trigger

TMR
D

= 1

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

reload and restart counting. Interrupt request IRQ

is generated on every end-of-

count.

T8 and T16 Timer Operation

The T8 timer is a programmable 8-bit counter/timer with two 8-bit capture regis-
ters and two 8-bit load registers. The T16 timer is a programmable 16-bit counter/
timer with one 16-bit capture register pair and one 16-bit load register pair. See
Figure 30. The T8 and T16 counters/timers have two modes of operation:

The transmit mode is used to generate complex waveforms. There are two
submodes:
The normal mode can be used in single-pass or modulo-N (repeating)

mode.

The ping-pong mode is used when the T8 timer counts down, enables the

T16 timer that counts down, enabling T8, and so on, until the mode is
disabled.

The demodulation mode is used to capture and demodulate complex
waveforms.

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

Figure 30. Counter/Timer Architecture

T8 Transmit Mode

Before T8 is enabled, the output of T8 depends on CTR1, D1. If CTR1, D1 is 0,
T8_OUT is 1. If CTR1, D1 is 1, T8_OUT is 0.

When T8 is enabled, the output T8_OUT switches to the initial value (CTR1 D1). If
the initial value (CTR1 D1) is 0, TC8L is loaded; otherwise, TC8H is loaded into
the counter. In single-pass mode (CTR0 D6), T8 counts down to 0 and stops,
T8_OUT toggles, the time-out status bit (CTR0 D5) is set, and a time-out interrupt
can be generated if it is enabled (CTR0 D1). In modulo-N mode, upon reaching
terminal count, T8_OUT is toggled, but no interrupt is generated. Then T8 loads a
new count (if T8_OUT level is 0), TC8L is loaded; if T8_OUT is 1, TC8H is loaded.

HI16

16-Bit

T16

8-Bit

Glitch

Filter

Edge

Detect

Circuit

LO16

And/Or

Logic

Timer
8/16

Timer 16

Timer 8

HI8

LO8

TC8H

TC8L

TC16H

TC16L

SCLK

Clock

Divider

T16 Clocked

Input

1 2 4 8

SCLK

Clock

Divider

T8 Clock Divider

1 2 4 8

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

T8 counts down to 0, toggles T8_OUT, sets the time-out status bit (CTR0 D5), and
generates an interrupt if enabled (CTR0 D1). This completes one cycle. T8 then
loads from TC8H or TC8L, according to the T8_OUT level, and repeats the cycle.

You can modify the values in TC8H or TC8L at any time.The new values take
effect when they are loaded. Do not write these registers at the time the values
are to be loaded into the counter/timer. An initial count of 1 is not allowed. An ini-
tial count of 0 causes TC8 to count from 0 to

FFh

FEh

. Transition from 0 to

FFh

is not a time-out condition (see Figure 31).

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

Do not use the same instructions for stopping the counter/
timers and setting the status bits. Two successive commands
are necessary--the first command for stopping counter/timers
and the second command for resetting the status bits--
because one counter/timer clock interval must complete for the
initiated event to actually occur.

T8 Demodulation Mode

Program TC8L and TC8H to

FFh

. After T8 is enabled, when the first edge (rising,

falling, or both, depending on CTR1 D5, D4) is detected, it starts to count down.
When a subsequent edge (rising, falling, or both, depending on CTR1 D5, D4) is
detected during counting, the current value of T8 is one's complemented and put
into one of the capture registers. If T8 is a positive edge, data is placed in LO8. If
T8 is a negative edge, data is placed in H18. One of the edge-detect status bits
(CTR1 D1, D0) is set, and an interrupt can be generated if enabled (CTR0 D2).
Meanwhile, T8 is loaded with TC8H and starts counting again. If T8 reaches 0, the
time-out status bit (CTR0 D5) is set, and an interrupt can be generated if enabled
(CTR0 D1), and T8 continues counting from

FFh

(see Figure 32).

Note:

Z86L972/Z86L973/Z86L974

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P R E L I M I N A R Y

T16 Transit Mode

In normal or ping-pong mode, the output of T16, when not enabled, is dependent
on CTR1, D0. If CTR1, D0 is a 0, T16_OUT is a 1; if CTR1, D0 is a 1, T16_OUT is
0. You can force the output of T16 to either a 0 or 1, whether it is enabled or not,
by programming CTR1 D3, D2 to a 10 or 11.

When T16 is enabled, TC16H * 256 + TC16L is loaded, and T16_OUT is switched
to its initial value (CTR1 d0). When T16 counts down to 0, T16_OUT is toggled (in
normal or ping-pong mode), an interrupt is generated if enabled (CTR2 D1), and a
status bit (CTR2 D5) is set. If it is in modulo-N mode, it is loaded with TC16H * 256
+ TC16L, and the counting continues.

You can modify the values in TC16H and TC16L at any time. The new values take
effect when they are loaded. Do not load these registers at the time the values are
to be loaded into the counter/timer. An initial count of 1 is not allowed. An initial
count of 0 causes T16 to count from 0 to

FFFFh

FFFEh

. Transition from 0 to

FFFFh

is not a time-out condition.

T16 Demodulation Mode

Program TC16L and TC16H to

FFh

. After T16 is enabled, when the first edge (ris-

ing, falling, or both, depending on CTR1 D5, D4) is detected, T16 captures HI16
and LO16, reloads, and begins counting.

Ping-Pong Mode

This operation mode is only valid in transmit mode. T8 and T16 must be pro-
grammed in single-pass mode (CTR0 D6, CTR2 D6), and ping-pong mode must
be programmed in CTR1 D3, D2. You can begin the operation by enabling either
T8 or T16 (CTR0 D7 or CTR2 D7). For example, if T8 is enabled, T8_OUT is set
to this initial value (CTR1 D1). According to T8_OUT's level, TC8H or TC8L is
loaded into T8. After the terminal count is reached, T8 is disabled, and T16 is
enabled. T16_OUT switches to its initial value (CTR1 D0), data from TC16H and
TC16L is loaded, and T16 starts to count. After T16 reaches the terminal count, it
stops. T8 is enabled again, and the whole cycle repeats. Interrupts can be allowed
when T8 or T16 reaches terminal control (CTR0 D1, CTR2 D1). To stop the ping-
pong operation, write 00 to bits D3 and D2 or CTR1.

Enabling ping-pong operation while the counters/timers are
running can cause intermittent counter/timer function. Disable
the counters/timers, then reset the status flags before starting
the ping-pong mode.

Note:

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

Control and Status Registers

The Z86L972/Z86L973/Z86L974 family has 4 I/O port registers, 33 status and
control registers, and 233 general-purpose RAM registers. The I/O port and con-
trol registers are included in the general-purpose register memory to allow any Z8
instruction to process I/O or control information directly, thus eliminating the
requirement for special I/O or control instructions. The Z8 instruction set permits
direct access to any of these 37 registers. In addition, each of the 233 general-
purpose registers can also function as an accumulator, an address pointer, or an
index register. Registers identified as "Reserved" do not exist or have not been
implemented in this design.

Register Summary

Table 10 through Table 13 summarize the name and location of all registers. The
register-by-register descriptions follow this section.

Table 10. I/O Port Registers (Group 0, Bank 0, Registers 0F)

Grp/Bnk Reg

Register Function

Identifier

(

00h

)

General-Purpose RAM Register

GPR

(

00h

)

General-Purpose RAM Register

GPR

(

00h

)

General-Purpose RAM Register

GPR

(

00h

)

General-Purpose RAM Register

GPR

(

00h

)

General-Purpose RAM Register

GPR

(

00h

)

General-Purpose RAM Register

GPR

(

00h

)

General-Purpose RAM Register

GPR

(

00h

)

General-Purpose RAM Register

GPR

(

00h

)

Reserved

(

00h

)

Port 6 Control Register

(

00h

)

Port 5 Control Register

(

00h

)

Port 4 Control Register

(

00h

)

Reserved

(

00h

)

Port 2 Control Register

(

00h

)

Reserved

(

00h

)

Reserved

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

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P R E L I M I N A R Y

Table 11. Control and Status Registers (Group F, Bank 0, Registers 0F)

Grp/Bnk Reg

Register Function

Identifier

(

F0h

)

Stack Pointer

(

F0h

)

General-purpose RAM Register

GPR

(

F0h

)

(

F0h

)

Program Control Flag Register

Flags

(

F0h

)

Interrupt Mask Register

IMR

(

F0h

)

Interrupt Request Register

IRQ

(

F0h

)

Interrupt Priority Register

IPR

(

F0h

)

Reserved

(

F0h

)

Port 3 Mode Register

P3M

(

F0h

)

Port 2 Mode Register

P2M

(

F0h

)

Reserved

(

F0h

)

Reserved

(

F0h

)

T1 Prescale Register

PRE1

(

F0h

)

T1 Data Register

(

F0h

)

T1 Mode Register

TMR

(

F0h

)

Reserved

Table 12. Timer Control Registers (Group 0, Bank D, Registers 0F)

Grp/Bnk Reg

Register Function

Identifier

(

0Dh

)

Reserved

(

0Dh

)

Reserved

(

0Dh

)

Reserved

(

0Dh

)

Low-Battery Detect Flag

(

0Dh

)

T16 MS-Byte Capture Register

HI8

(

0Dh

)

T16 LS-Byte Capture Register

LO8

(

0Dh

)

T8 High Capture Register

HI16

(

0Dh

)

T8 Low Capture Register

LO16

(

0Dh

)

T16 MS-Byte Hold Register

TC16H

(

0Dh

)

T16 LS-Byte Hold Register

TC16L

(

0Dh

)

T8 High Hold Register

TC8H

(

0Dh

)

T8 Low Hold Register

TC8L

(

0Dh

)

T8/T16 Control Register B

CTR3

(

0Dh

)

T16 Control Register

CTR2

(

0Dh

)

T8/T16 Control Register A

CTR1

(

0Dh

)

T8 Control Register

CTR0

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

Register Error Conditions

Registers in the Z8 Standard Register File must be used correctly because certain
conditions produce inconsistent results and must be avoided.

Registers

F5h

F9h

are write-only registers. If an attempt is made to read these

registers,

FFh

is returned. Reading any write-only register returns

FFh

When the Register Pointer (register FDH) is read, the least significant four bits
(lower nibble) indicate the current Expanded Register File Bank. (For
example, 0000 indicates the Standard Register File, while 1010 indicates
Expanded Register File Bank A.)

Writing to bits that are selected as timer outputs changes the I/O register but
has no effect on the pin signal.

The Z8 instruction DJNZ uses any general-purpose working register as a
counter.

Logical instructions such as OR and AND require that the current contents of
the operand be read. They do not function properly on write-only registers.

Table 13. SMR and Port Mode Registers (Group 0, Bank F, Registers 0F)

Grp/Bnk Reg

Register Function

Identifier

(

0Fh

)

Reserved

(

0Fh

)

Reserved

(

0Fh

)

Reserved

(

0Fh

)

Reserved

(

0Fh

)

Stop Mode Recovery Register

SMR

(

0Fh

)

Reserved

(

0Fh

)

Reserved

(

0Fh

)

Reserved

(

0Fh

)

Reserved

(

0Fh

)

Port 6 Mode

P6M

(

0Fh

)

Port 5 Stop Mode Recovery

P5SMR

(

0Fh

)

Port 5 Mode Register

P5M

(

0Fh

)

Reserved

(

0Fh

)

Port 4 Mode Register

P4M

(

0Fh

)

Port 2 Stop Mode Recovery

P2SMR

(

0Fh

)

Port Configuration Register

P456CON

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

Registers (Grouped by Function)

The following is a summary of the 37 special-purpose registers of the Z86L972/
Z86L973/Z86L974 family grouped by function. The following are the functional
groups:

Flags and Pointers

Interrupt Control

I/O Port Control

Timer Control--General-Purpose Timer (T1)

Timer Control--T8 and T16 Timers

Stop-Mode Recovery Control

For any of the registers described in this section (see Table 14), bits identified as
"Reserved" either do not exist (meaning they have not been implemented in this
design) or have a special purpose in a ZiLOG engineering or test environment.

Do not attempt to use these bits as the results are
unpredictable and meaningless.

Table 14. Register Description Locations

Address
Grp/Bnk Register

Register Function

Symbol

Location

00h

r2 (R2)

Port 2 Data

page 61

00h

r4 (R4)

Port 4 Data

page 62

00h

r5 (R5)

Port 5 Data

page 62

00h

r6 (R6)

Port 6 Data

page 64

0Dh

T8 Timer Control

CTR0

page 70

0Dh

T8/T16 Control (A)

CTR1

page 67

0Dh

T16 Timer Control

CTR2

page 73

0Dh

T8/T16 Control (B)

CTR3

page 69

0Dh

T8 Low Load

TC8L

page 72

0Dh

T8 High Load

TC8H

page 72

0Dh

T16 Low Load

TC16L

page 75

0Dh

T16 High Load

TC16H

page 75

0Dh

T16 Low Capture

LO16

page 74

0Dh

T16 High Capture

HI16

page 74

0Dh

r10

T8 Low Capture

LO8

page 71

0Dh

r11

T8 High Capture

HI8

page 71

Caution:

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

Flags and Pointer Registers

In addition to the three standard Z8 flag and pointer registers (Program Control
Register Pointer, and Stack Pointer), the Z86L972/Z86L973/Z86L974 family
includes a Low-Battery Detect Flag register.

0Dh

r12

Low Battery Detect

page 55

0Fh

Port Configuration (A)

P456CON

page 59

0Fh

Port 2 SMR Source

P2SMR

page 77

0Fh

Port 4 Mode

P4M

page 62

0Fh

Port 5 Mode

P5M

page 62

0Fh

Port 5 SMR Source

P5SMR

page 77

0Fh

Port 6 Mode

P6M

page 64

0Fh

r11

Stop Mode Recovery

SMR

page 76

F0h

r1 (R241)

T1 Timer Mode

TMR

page 65

F0h

r2 (R242)

T1 Timer Data

page 65

F0h

r3 (R243)

T1 Timer Prescale

PRE1

page 66

F0h

r6 (R246)

Port 2 Mode

P2M

page 61

F0h

r7 (R247)

Port Configuration (B)

P3M

page 59

F0h

r9 (R249)

Interrupt Priority

IPR

page 57

F0h

r10 (R250)

Interrupt Request

IRQ

page 58

F0h

r11 (R251)

Interrupt Mask

IMR

page 56

F0h

r12 (R252)

Program Control Flags Flags

page 52

F0h

r13 (R253)

page 53

F0h

r15 (R255)

Stack Pointer

page 54

Note:

This register is not reset following Stop Mode Recovery (SMR).

Table 14. Register Description Locations (Continued)

Address
Grp/Bnk Register

Register Function

Symbol

Location

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

Program Control Flag Register (Flags)

The Program Control Flag register (see Table 15) reflects the current status of the
Z8 as shown in Table 15. The FLAGS register contains six bits of status informa-
tion that are set or cleared by CPU operations. Four of the bits (C, V, Z, and S) can
be tested for use with conditional jump instructions. Two flags (H and D) cannot be
tested and are used for BCD arithmetic. The two remaining flags in the register
(F1 and F2) are available to you, but they must be set or cleared by instructions
and are not usable with conditional jumps.

Table 15. FLAGS Register [Group/Bank F0h, Register C (R252)]

Bit

Bit/Field

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

7_______

Carry Flag (C)

R/W

Indicates the "carry out" of bit 7
position of a register being used as
an accumulator; on Rotate and Shift
instructions this bit contains the most
recent value shifted out of the
specified register

_6______

Zero Flag (Z)

R/W

Indicates that the contents of an
accumulator register is zero following
an arithmetic or logical operation

__5_____

Sign Flag (S)

R/W

Stores the value of the most
significant bit of a result following an
arithmetic, logical, Rotate, or Shift
operation; in arithmetic operations on
signed numbers, a positive number is
identified by a 0, and a negative
number is identified by a 1

___4____

Overflow
Flag (V)

R/W

For signed arithmetic, Rotate, and
Shift operations, the flag is set to 1
when the result is greater than the
maximum possible number (>127) or
less than the minimum possible
number (<-128) that can be
represented in two's complement
form; following logical operations, this
flag is set to 0

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

Register Pointer (RP)

Z8 instructions can access registers directly or indirectly using either a 4-bit or 8-
bit address field. The upper nibble of the Register Pointer, as described in
Table 16, contains the base address of the active Working Register GROUP. The
lower nibble contains the base address of the Expanded Register File BANK.
When using 4-bit addressing, the 4-bit address of the working register (r0 to rF) is
combined with the upper nibble of the Register Pointer (identifying the WR
GROUP), thus forming the 8-bit actual address.

____3___

Decimal Adjust
Flag (D)

R/W

1
0

Used for BCD arithmetic--after a
subtraction, the flag is set to 1;
following an addition, it is cleared to 0

_____2__

Half Carry
Flag (H)

R/W

1
0

Set to 1, whenever an addition
generates a "carry out" of bit position
3 (overflow) of an accumulator; or
subtraction generates a "borrow into"
bit 3

______1_

User Flag (F2)

R/W

1
0

User definable

_______0

User Flag (F1)

R/W

1
0

User definable

Table 16. RP Register [Group/Bank F0h, Register D (R253)]

Bit

Bit/Field

Working Register Group

Expanded Register File Bank

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

7654_____

Working Register
Group Pointer

R/W

Identifies 1 of 16 possible WR
Groups, each containing 16 Working
Registers

_____3210

Expanded
Register File
Bank Pointer

R/W

Identifies 1 of 16 possible ERF
Banks; only Banks 0, D, and F are
valid for the Z86L972/Z86L973/
Z86L974 family

Table 15. FLAGS Register [Group/Bank F0h, Register C (R252)] (Continued)

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

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P R E L I M I N A R Y

Stack Pointer (SP)

The Z86L972/Z86L973/Z86L974 family of products is configured for an internal
stack. The size of the stack is limited only by the available memory space or gen-
eral-purpose RAM registers dedicated to this task. An 8-bit stack pointer, as
described in Table 17, is used for all stack operations.

Table 17. SP Register [Group/Bank F0h, Register F (R255)]

Bit

Bit/Field

Stack Pointer

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

76543210

Stack Pointer

R/W

Points to the data stored on the top of
the stack; an overflow or underflow
can occur if the stack address is
incremented or decremented during
normal stack operations

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

Low-Battery Detect Flag (LB)

When the Z86L972/Z86L973/Z86L974 is used in a battery-operated application,
one of the on-chip comparators can be used to check that the V

is at the

required level for correct operation of the device. When voltage begins to
approach the V

point, an on-chip low-battery detection circuit is tripped, which

in turn sets a user-readable flag. The low-voltage detection level (V

) is set to

+ 0.4 V. The LB register, as described in Table 18, is used to set and reset the

LB flag.

Interrupt Control Registers

The Z8 allows up to six different interrupts from a variety of sources. These inter-
rupts can be masked and their priorities set by using the Interrupt Mask Register
and Interrupt Priority Register. The Interrupt Request Register stores the interrupt
requests for both vectored and polled interrupts.

Table 18. LB Register (Group/Bank 0Dh, Register C)

Bit

Bit/Field

Reserved

Pad
LVD

LVD_
Flag

LVD_
Enable

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

76543___

Reserved

R
W

1
X

Always reads

11111

No Effect

_____2__

Pad LVD

Pad is not regulated when P43=0
(V

pad

min

; see page 28)

Pad is regulating the current when
P43=0 (V

pad

min

; see page 28)

Reset Pad LB flag

______1_

LVD_Flag

R
R
W

1
0
X

LB Flag Set if

LB Flag Reset
No Effect

_______0

LVD_Enable

R/W

1
0

Enable LB *
Disable LB

Note: * When LVD is enabled, IRQ5 is set only for low-voltage detection. Timer 1 will not generate
an interrupt request.

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

Interrupt Mask Register

The IMR, as described in Table 19, individually or globally enables the six interrupt
requests. Bit 7 of the IMR is the master enable and must be set before any of the
individual interrupt requests can be recognized. Bit 7 must be set and reset by the
enable interrupts and disable interrupts instructions only. The IMR is automatically
reset during an interrupt service routine and set following the execution of an
Interrupt Return (IRET) instruction.

Bit 7 must be reset by the DI instruction before the contents of
the Interrupt Mask Register or the Interrupt Priority Register are
changed except in the following situations:

Immediately after a hardware reset
Immediately after executing an interrupt service routine and before IMR bit

7 has been set by any instruction

Table 19. IMR (Group/Bank 0Fh, Register B)

Bit

Bit/Field

Master

Re-
served IRQ5

IRQ4

IRQ3

IRQ2

IRQ1

IRQ0

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

7_______

Master

R/W

1
0

Enable Master Interrupt
Disable Master Interrupt

_6______

Reserved

R
W

1
X

Always reads

No Effect

__5_____

IRQ

R/W

1
0

Enable IRQ

Disable IRQ

___4____

IRQ

R/W

1
0

Enable IRQ

Disable IRQ

____3___

IRQ

R/W

1
0

Enable IRQ

Disable IRQ

_____2__

IRQ

R/W

1
0

Enable IRQ

Disable IRQ

______1_

IRQ

R/W

1
0

Enable IRQ

Disable IRQ

_______0

IRQ

R/W

1
0

Enable IRQ

Disable IRQ

Note:

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

Interrupt Priority Register (IPR)

The IPR, as described in Table 20, is a write-only register that sets priorities for
the vectored interrupts in order to resolve simultaneous interrupt requests. There
are 48 sequence possibilities for interrupts. The six interrupts, IRQ

to IRQ

, are

divided into three groups of two interrupt requests each, as follows:

Group A consists of IRQ

and IRQ

Group B consists of IRQ

and IRQ

Group C consists of IRQ

and IRQ

)

Priorities can be set both within and between groups using the IPR. Bits 1, 2, and
5 of the IPR define the priority of individual members within the groups. Bits 0, 3,
and 4 are encoded to define six priority orders between the three groups. Bits 6
and 7 are reserved.

Table 20. IPR (Group/Bank 0Fh, Register 9)

Bit

Bit/Field

Reserved

Grp A
IRQ3_5 Int_Group

Grp B
IRQ0_2

Grp C
IRQ1_4

Int_
Group

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

76______

Reserved

No Effect

__5_____

Grp A Priority:
IRQ

and IRQ

1
0

IRQ

>IRQ

(Group A)

IRQ

>IRQ

___43__0

Interrupt Group
Priority

111
110
101
100
011
010
001
000

Reserved
B>A>C
C>B>A
B>C>A
A>C>B
A>B>C
C>A>B
Reserved

_____2__

Grp B Priority:
IRQ

and IRQ

1
0

IRQ

>IRQ

(Group B)

IRQ

>IRQ

______1_

Grp C Priority:
IRQ

and IRQ

1
0

IRQ

>IRQ

(Group C)

IRQ

>IRQ

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

Interrupt Request Register

The IRQ, as described in Table 21, is a read/write register that stores the interrupt
requests for both vectored and polled interrupts. When an interrupt request is
made by any of the six interrupts, the corresponding bit in the IRQ is set to 1.

Table 21. IRQ (Group/Bank 0Fh, Register A)

Bit

Bit/Field

Interrupt Edge

Set
IRQ5

Set
IRQ4

Set
IRQ3

Set
IRQ2

Set
IRQ1

Set
IRQ0

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

76______

Interrupt Edge
Trigger

R/W

11
10
01
00

P51 Rise/FallingP52 Rise/Falling
P51 Rising P52 Falling
P51 FallingP52 Rising
P51 FallingP52 Falling

__5_____

Set IRQ

R
R
W
W

1
0
1
0

IRQ

Inactive

IRQ

Active

Set IRQ

Reset IRQ

___4____

Set IRQ

R
R
W
W

1
0
1
0

IRQ

Inactive

IRQ

Active

Set IRQ

Reset IRQ

____3___

Set IRQ

R
R
W
W

1
0
1
0

IRQ

Inactive

IRQ

Active

Set IRQ

Reset IRQ

_____2__

Set IRQ

R
R
W
W

1
0
1
0

IRQ

Inactive

IRQ

Active

Set IRQ

Reset IRQ

______1_

Set IRQ

R
R
W
W

1
0
1
0

IRQ

Inactive

IRQ

Active

Set IRQ

Reset IRQ

_______0

Set IRQ

R
R
W
W

1
0
1
0

IRQ

Inactive

IRQ

Active

Set IRQ

Reset IRQ

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

Whenever a power-on reset is executed, the IRQ is reset to

00h

and disabled.

Before the IRQ accepts requests, it must be enabled by executing an enable inter-
rupts instruction.

IRQ is always cleared to

00h

and is in read-only mode until the

first EI instruction that enables the IRQ to be read/write. Setting
the Global Interrupt Enable bit in the Interrupt Mask Register
(IMR bit 7) does not enable the IRQ. Execution of an EI
instruction is required.

For polled processing, IRQ must be initialized by an EI instruction. To properly ini-
tialize the IRQ, the following code is provided:

CLR

IMR ; make sure vectored interrupts are disabled

; enable IRQ, otherwise it is read only

; not necessary, if interrupts were previously

; enabled

; disable interrupt handling

IMR is cleared before the IRQ enabling sequence to ensure no unexpected inter-
rupts occur when EI is executed. This code sequence must be executed before
programming the application required values for IPR and IMR.

I/O Port Control Registers

Each of the four ports (Ports 2, 4, 5, and 6) has an input register, an output regis-
ter, and an associated buffer and control logic. Because there are separate input
and output registers associated with each port, writing bits defined as inputs
stores the data in the output register. This data cannot be read as long as the bits
are defined as inputs. However, if the bits are reconfigured as output, the data
stored in the output register is reflected on the output pins and can then be read.
This mechanism allows you to initialize the outputs before driving their loads.

Port Configuration Registers (P456CON and P3M)

The port configuration register (described in Table 22) switches the comparator
inputs from digital to analog and allows Ports 4, 5, and/or 6 to be switched from
push/pull active outputs to open drain outputs. In ZiLOG Test Mode, bit 3 of this
register is used to enable the Address Strobe/Data Strobe. Bit 3 is not available in
User Mode.

Note:

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

Port 2 outputs are configured using the P3M Register, shown in Table 23. Bit 0 of
the P3M Register switches Port 2 from push/pull active to open drain outputs. No
other bits in this register are implemented.

Table 22. P456CON Register (Group/Bank 0Fh, Register 0)

Bit

Bit/Field

Not Used

P51_
Mode

P52_
Mode

Reserved

P6_
Output

P5_
Output

P4_
Output

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

76______

Not Used

R/W

These bits exist but do not have any
function assigned to them; they are
reserved for future extensions and must
not be used.

__5_____

Comparator 1
Mode

R/W

1
0

Analog (P50, P51 as Inputs)
Digital inputs

___4____

Comparator 2
Mode

R/W

1
0

Analog comparator inputs (P52, P53
configured as Inputs)
Digital inputs

____3___

Reserved

_____2__

Port 6 Output
Configuration

1
0

Push-Pull Active
Open Drain Outputs
Always reads back

______1_

Port 5 Output
Configuration

1
0

Push-Pull Active
Open Drain Outputs
Always reads back

_______0

Port 4 Output
Configuration

1
0

Push-Pull Active
Open Drain Outputs
Always reads back

Note: *Do not use the read-modify-write instructions (for example, OR and AND) with this register.
Bits 0, 1, and 2 always read back 1.
Note:

P43 can never be configured as push-pull. After any reset, P43 is configured as tristate high

impedance.

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

Port 2 Control and Mode Registers (P2 and P2M)

Port 2 is a general-purpose 8-bit, bidirectional I/O port, as shown in Table 24.
Each of the eight Port 2 I/O lines can be independently programmed as either
input or output using the Port 2 Mode Register (see Table 25.)

Table 23. P3M Register [Group/Bank F0h, Register 7 (R247)]

Bit

Bit/Field

Reserved

P2_
Output

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

7654321_

Reserved

R
W

1
X

Always reads

1111111

No Effect

_________0 Port 2 Output

Configuration

1
0

Push-Pull Active
Open Drain Outputs

Table 24. P2 Register [Group/Bank 00h, Register 2 (R2)]

Bit

Bit/Field

Port 2 Data

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

76543210

Port 2 Data

R/W

Data

Port 2 Input/Output Register

Table 25. P2M Register [Group/Bank F0h, Register 6 (R246)]

Bit

Bit/Field

P27M

P26M

P25M

P24M

P23M

P22M

P21M

P20M

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

76543210
(by bit)

Port 2 Mode
Select

R
W
W

1
1
0

Always reads

11111111

Input
Output

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

A bit set to 1 in the P2M Register configures the corresponding bit in Port 2 as an
input, while a bit set to 0 configures an output line.

Port 4 Control and Mode Registers (P4 and P4M)

Port 4 is a general-purpose 8-bit, bidirectional I/O port, as shown in Table 26.
Each of the eight Port 4 I/O lines can be independently programmed as either
input or output using the Port 4 Mode Register (see Table 27.)

A bit set to 1 in the P4M Register configures the corresponding bit in Port 4 as an
input, while a bit set to 0 configures an output line.

P43, the controlled current output pad, cannot be configured as
an input. (P43 read = P43 out)

Port 5 Control and Mode Registers (P5 and P5M)

Port 5 is a general-purpose 8-bit, bidirectional I/O port, as shown in Table 28.
Each of the eight Port 5 I/O lines can be independently programmed as either
input or output using the Port 5 Mode Register (see Table 29.)

Table 26. P4 Register [Group/Bank 00h, Register 4 (R4)]

Bit

Bit/Field

Port 4 Data

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

76543210

Port 4 Data

R/W

Data

Port 4 Input/Output Register

Table 27. P4M Register (Group/Bank 0Fh, Register 2)

Bit

Bit/Field

P47M

P46M

P45M

P44M

P43M

P42M

P41M

P40M

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

7654_210
(by bit)

Port 4 Mode
Select

R/W

1
0

Input
Output

____3___

P43
Mode Select

R/W

0
1

Output
Tristate High Impedance

Note:

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

A bit set to a 1 in the P5M Register configures the corresponding bit in Port 5 as
an input, while a bit set to 0 configures an output line.

Regardless of how P5M bits 2 and 3 are set, P52 and P53 are
always in input mode.

Table 28. P5 Register [Group/Bank 00h, Register 5 (R5)]

Bit

Bit/Field

Port 5 Data

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

76543210

Port 5 Data

R/W

Data

Port 5 Input/Output Register

Table 29. P5M Register (Group/Bank 0Fh, Register 4)

Bit

Bit/Field

P57M

P56M

P55M

P54M

P53M

P52M

P51M

P50M

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

7654__10
(by bit)

Port 5 Mode
Select

R/W

1
0

Input
Output

____32__

P53, P52
Mode Select

R/W

Input
Regardless of what is written to this
pin, P53 and P52 are always in input
mode.

Note:

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

Port 6 Control and Mode Registers (P6 and P6M)

Port 6 is a general-purpose 8-bit, bidirectional I/O port, as shown in Table 30.
Each of the eight Port 6 I/O lines can be independently programmed as either
input or output using the Port 6 Mode Register (see Table 31.)

A bit set to 1 in the P6M Register configures the corresponding bit in Port 6 as an
input, while a bit set to 0 configures an output line.

Timer Control Registers--General-Purpose Timer (T1)

The Z86L972/Z86L973/Z86L974 family provides one standard 8-bit Z8 counter/
timer, T1, driven by its own 6-bit prescaler, PRE1. T1 is independent of the pro-
cessor instruction sequence, relieving software from time-critical operations such
as interval timing or event counting. There are three registers that control the
operation of T1: T1 Data Register (T1), T1 Mode Register (TMR), and T1 Prescale
Register (PRE1). Because the timer, prescaler, and mode register are mapped
into the standard Z8 register file, the software can treat the counter/timer as a gen-
eral-purpose register, thus eliminating the requirement for special instructions.

Table 30. P6 Register [Group/Bank 00h, Register 6 (R6)]

Bit

Bit/Field

Port 6 Data

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

76543210

Port 6 Data

R/W

Data

Port 6 Input/Output Register

Table 31. P6M Register (Group/Bank 0Fh, Register 6)

Bit

Bit/Field

P67M

P66M

P65M

P64M

P63M

P62M

P61M

P60M

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

76543210
(by bit)

Port 6 Mode
Select

R/W

1
0

Input
Output

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

T1 Data Register (T1)

The counter/timer register (T1) consists of an 8-bit down counter, a write-only reg-
ister that holds the initial count value, and a read-only register that holds the cur-
rent count value. The initial value of T1 can range from 1 to 255 (0 represents
256) (see Table 32.)

T1 Mode Register (TMR)

Under software control, T1 counter/timer is started and stopped using the T1
Mode Register as shown in Table 33.

Table 32. T1 Register [Group/Bank F0h, Register 2 (R242)]

Bit

Bit/Field

T1_Value

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate

Bit
Position

Bit/Field

R/W

Value

Description

76543210

Value

R
W

Data
Data

Current Value
Initial Value (Range 1 to 256 Decimal)

Table 33. TMR Register [Group/Bank F0h, Register 1 (R241)]

Bit

Bit/Field

TOUT_Mode

TIN_Mode

T1_
Count

T1_
Load

Reserved

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

76______

OUT

Mode

R/W

11
10
01
00

Internal Clock OUT on P56
T

OUT on P56

Reserved
Not used (P56 configured as I/O)

__54____

Mode

R/W

11
10
01
00

Trigger Input (Retriggerable)
Trigger Input (Not-retriggerable)
Gate Input
External Clock Input (T

on P52)

____3___

Count

R/W

1
0

Enable T

Count

Disable T

Count

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

T1 Prescale Register (PRE1)

The T1 prescaler consists of an 8-bit register and a 6-bit down-counter. The six
most significant bits (D2D7) of PRE1 hold the prescaler's count modulo, a value
from 1 to 64 decimal, as shown in Table 34. The prescale register also contains
control bits that specify the counting mode and clock source for T1.

Timer Control Registers--T8 and T16 Timers

One of the unique features of the Z86L972/Z86L973/Z86L974 family is a special
timer architecture to automate the generation and reception of complex pulses or
signals. This timer architecture consists of one programmable 8-bit counter timer
with two capture registers and two load registers and a programmable 16-bit
counter/timer with one 16-bit capture register pair and one 16-bit load register pair
and their associated control registers. These counter/timers can work indepen-
dently or can be combined together using a number of user-selectable modes
governed by the T8/T16 control registers.

_____2__

Load

R/W

1
0

Load T

No effect

______10

Reserved

R
W

1
X

Always reads

No effect

Table 34. PRE1 Register [Group/Bank F0h, Register 3 (R243)]

Bit

Bit/Field

Prescaler_Modulo

Clock_
Source

Count_
Mode

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

765432__

Prescaler Modulo R/W

Data

Range: 1 to 64 Decimal

_______1_

Clock Source

R/W

1
0

Internal

External (T

on P52)

________0

Count Mode

R/W

1
0

Modulo-n

Single Pass

Table 33. TMR Register [Group/Bank F0h, Register 1 (R241)] (Continued)

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

T8/T16 Control Register A (CTR1)

The T8/T16 Control Register A controls the functions in common with both the T

and T

counter/timers. The T

and T

counter/timers have two primary modes of

operation: Transmit Mode and Demodulation Mode. Transmit Mode is used for
generating complex waveforms. The Transmit Mode has two submodes: Normal
Mode and Ping-Pong Mode. The settings for CTR1 in Transmit Mode are given in
Table 35.

Table 35. CTR1 Register (In Transmit Mode) (Group/Bank 0Dh, Register 1)

Bit

Bit/Field

Mode

P43
Out

T8/T16_Logic

Transmit_
Submode

Initial_
T8_Out

Initial_
T16_
Out

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

7_______

Mode

R/W

1
0

Demodulation
Transmit

_6______

P43_Out

R/W

1
0

P43 configured as T8/T16 Output
P43 configured as I/O

__54____

Logic

R/W

11
10
01
00

NAND
NOR
OR
AND

____32__

Transmit_
Submode

R/W

11
10
01
00

T16_Out = 1
T16_Out = 0
Ping-Pong Mode
Normal Operation

______1_

Initial_T8_Out

R/W

1
0

T8_Out set to 1 initially
T8_Out set to 0 initially

_______0

Initial_T16_Out

R/W

1
0

T16_Out set to 1 initially
T16_Out set to 0 initially

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

In Demodulation Mode, the T8 and T16 counter/timers are used to capture and
demodulate complex waveforms. The settings for CTR1 in Demodulation Mode
are given in Table 36.

Table 36. CTR1 Register (in Demodulation Mode) (Group/Bank 0Dh, Register 1)

Bit

Bit/Field

Mode

Demod
_Input

Edge_Detect

Glitch_Filter

Rising
Edge

Falling
Edge

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

7_______

Mode

R/W

1
0

Demodulation
Transmit

_6______

Demodulator_
Input

R/W

1
0

P20 as Demodulator Input
P51 as Demodulator Input

__54____

Edge_Detect

R/W

11
10
01
00

Reserved
Both Edges
Rising Edge
Falling Edge

____32__

Glitch_Filter

R/W

11
10
01
00

16 SCLK Cycles
8 SCLK Cycles
4 SCLK Cycles
No Filter

______1_

Rising_Edge

R
R
W
W

1
0
1
0

Rising Edge Detected
No Rising Edge
Reset Flag to 0
No Effect

_______0

Falling_Edge

R
R
W
W

1
0
1
0

Falling Edge Detected
No Falling Edge
Reset Flag to 0
No Effect

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

T8/T16 Control Register B (CTR3)

The T8/T16 Control Register B, known as CTR3, is a new register to the Z86L972/
Z86L973/Z86L974 family. This register allows the T

and T

counters to be syn-

chronized. The settings of CTR3 are described in Table 37.

Table 37. CTR3 Register (Group/Bank 0Dh, Register 3)

Bit

Bit/Field

T16_
Enable

T8_
Enable

Sync
Mode

Reserved

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

7_______

Enable

R
R
W
W

1
0
1
0

Counter Enabled
Counter Disabled
Enable Counter
Stop Counter

_6______

Enable

R
R
W
W

1
0
1
0

Counter Enabled
Counter Disabled
Enable Counter
Stop Counter

__5_____

Sync Mode

R/W

1
0

Enable Sync Mode
Diable Sync Mode

___43210

Reserved

R
W

1
X

Always reads

11111

No Effect

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

T8 Control Register (CTR0)

As shown in Table 38, the T8 Control Register, known as CTR0, controls the oper-
ation of the 8-bit T

timer.

Table 38. CTR0 Register (Group/Bank 0Dh, Register 0)

Bit

Bit/Field

T8_
Enable

Single/
Mod-
ulo-n

Time_
Out

T8_Clock

Capture
INT_
Mask

Counter
INT_
Mask

P40_
Out

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

7_______

Enable

R
R
W
W

1
0
1
0

Counter Enabled
Counter Disabled
Enable Counter
Stop Counter

_6______

Single/
Modulo-n

R/W

1
0

Single Pass
Modulo-n

__5_____

Time_Out

R
R
W
W

1
0
1
0

Counter Timeout Occurred
No Counter Timeout
Reset Flag to 0
No Effect

___43___

Clock

R/W

11
10
01
00

SCLK/8
SCLK/4
SCLK/2
SCLK

_____2__

Capture Interrupt
Mask

R/W

1
0

Enable Data Capture Interrupt
Disable Data Capture Interrupt

______1_

Counter Interrupt
Mask

R/W

1
0

Enable Time_Out Interrupt
Disable Time_Out Interrupt

_______0

P40_Out

R/W

1
0

P40 configured as T

Output

P40 configured as I/O

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

T8 High Capture Register (HI8)

The T8 High Capture Register, as described in Table 39, holds the captured data
from the output of the T

counter/timer. This register is typically used to hold the

number of counts when the input signal is high (or

T8 Low Capture Register (LO8)

The T8 Low Capture Register, as described in Table 40, holds the captured data
from the output of the T

counter/timer. This register is typically used to hold the

number of counts when the input signal is low (or

Table 39. HI8 Register (Group/Bank 0Dh, Register B)

Bit

Bit/Field

T8_Capture_HI

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

76543210

Capture

High Value

R
W

Data

Captured Data
No Effect

Table 40. LO8 Register (Group/Bank 0Dh, Register A)

Bit

Bit/Field

T8_Capture_LO

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

76543210

Capture

Low Value

R
W

Data

Captured Data
No Effect

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

T8 High Load Register (TC8H)

The T8 High Load Register, as described in Table 41, is loaded with the counter
value necessary to keep the T8_Out signal in the high state for the required time.

T8 Low Load Register (TC8L)

The T8 Low Load Register, as described in Table 42, is loaded with the counter
value necessary to keep the T8_Out signal in the low state for the required time.

Table 41. TC8H Register (Group/Bank 0Dh, Register 5)

Bit

Bit/Field

T8_Level_HI

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

76543210

Level

High Value

R/W

Data

Duration that T8_Out remains High

Table 42. TC8L Register (Group/Bank 0Dh, Register 4)

Bit

Bit/Field

T8_Level_LO

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

76543210

Level

Low Value

R/W

Data

Duration that T8_Out remains Low

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

T16 Control Register (CTR2)

The T16 Control Register, known as CTR2, controls the operation of the 16-bit T

timer (see Table 43).

Table 43. CTR2 Register (Group/Bank 0Dh, Register 2)

Bit

Bit/Field

T16_
Enable

Single/
Mod-
ulo-n

Time_
Out

T16_Clock

Capture
INT_
Mask

Counter
INT_
Mask

P41_
Out

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

7_______

Enable

R
R
W
W

1
0
1
0

Counter Enabled
Counter Disabled
Enable Counter
Stop Counter

_6______

Single/
Modulo-n

R/W

1
0

In Transmit Mode:
Single Pass
Modulo-n
In Demodulation Mode:
T

Does Not Recognize Edge

Recognizes Edge

__5_____

Time_Out

R
R
W
W

1
0
1
0

Counter Timeout Occurred
No Counter Timeout
Reset Flag to 0
No Effect

___43___

Clock

R/W

11
10
01
00

SCLK/8
SCLK/4
SCLK/2
SCLK

_____2__

Capture Interrupt
Mask

R/W

1
0

Enable Data Capture Interrupt
Disable Data Capture Interrupt

______1_

Counter Interrupt
Mask

R/W

1
0

Enable Time_Out Interrupt
Disable Time_Out Interrupt

_______0

P41_Out

R/W

1
0

P41 configured as T

Output

P41 configured as I/O

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

T16 MS-Byte Capture Register (HI16)

The T16 MS-Byte Capture Register, as described in Table 44, holds the captured
data from the output of the T

counter/timer. This register holds the most signifi-

cant byte of the data.

T16 LS-Byte Capture Register (LO16)

The T16 LS-Byte Capture Register, as described in Table 45, holds the captured
data from the output of the T

counter/timer. This register holds the least signifi-

cant byte of the data.

Table 44. HI16 Register (Group/Bank 0Dh, Register 9)

Bit

Bit/Field

T16_Capture_HI

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

76543210

Capture HI

R
W

Data

MS-Byte of Captured Data
No Effect

Table 45. LO16 Register (Group/Bank 0Dh, Register 8)

Bit

Bit/Field

T16_Capture_LO

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

76543210

Capture LO

R
W

Data

LS-Byte of Captured Data
No Effect

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

T16 MS-Byte Load Register (TC16H)

The T16 MS-Byte Load Register, as described in Table 46, is loaded with the most
significant byte of the T

counter value.

T16 LS-Byte Load Register (TC16L)

The T16 LS-Byte Load Register, as described in Table 47, is loaded with the least
significant byte of the T

counter value.

Stop-Mode Recovery Control Registers

The Z86L972/Z86L973/Z86L974 family of products allows 16 individual I/O pins
(Ports 2 and 5) to be used as a stop-mode recovery sources. The STOP mode is
exited when one of these SMR sources is toggled.

Table 46. TC16H Register (Group/Bank 0Dh, Register 7)

Bit

Bit/Field

T16_Data_HI

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

76543210

Data HI

R/W

Data

MS-Byte of the T

Counter

Table 47. TC16L Register (Group/Bank 0Dh, Register 6)

Bit

Bit/Field

T16_Data_LO

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

76543210

Data LO

R/W

Data

LS-Byte of the T

Counter

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

Stop-Mode Recovery Register

The SMR register serves two functions. Bit D7 of the SMR register, as shown in
Table 48, is the Stop Mode Flag that is set upon entering stop mode. A 0 in this bit
indicates that the device has been reset by a POR or WDT Reset. A POR or WDT
Reset is sometimes referred to as a "cold" start. A 1 in bit D7 indicates that the
device was awakened by a SMR source. Waking a device with a SMR source is
sometimes referred to as a "warm" start.

The Stop Mode Recovery source can be selected by any combination of P2 and
P5 by P2SMR and P5SMR, respectively. If the pin is selected as the SMR source,
its logic level is latched into a register. A wait up signal is generated if its logic level
changes. This applies to all selected pins for the SMR source.

The comparators of P5 cannot be used as an SMR source. The comparator is
turned off in STOP mode.

The second function of the SMR register is the selection of the external clock
divide value. The purpose of this control is to selectively reduce device power con-

Table 48. SMR Register (Group/Bank 0Fh, Register B)

Bit

Bit/Field

Stop
Flag

Re-
served

Stop
Delay

Reserved

SCLK Select

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

7_______

Stop Mode Flag

R
R
W

1
0
X

Stop Recovery (warm start)
POR/WDT Reset (cold start)
No Effect

_6______

Reserved

R
W

1
X

Always reads

No Effect

__5_____

Stop Delay

R
W
W

1
1
0

Always reads

Enable 5ms /Reset delay
Disable /Reset delay after SMR

___432__

Reserved

R
W

1
X

Always reads

111

No Effect

_______10

System Clock
Select

R
W
W
W
W

11
11
10
01
00

Always reads

SCLK, TCLK = XTAL/16
SCLK, TCLK = XTAL
SCLK, TCLK = XTAL/32
SCLK, TCLK = XTAL/2

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

sumption during normal processor execution (SCLK control) and/or HALT mode
(where TCLK sources counter/timers and interrupt logic).

Port 2 Stop Mode Recovery (P2SMR)

The P2SMR register, as described in Table 49, defines which I/O lines in Port 2
are to be used as stop mode recovery sources.

Port 5 Stop-Mode Recovery (P5SMR)

The P5SMR register, as described in Table 50, defines which I/O lines in Port 5
are to be used as stop-mode recovery sources.

Table 49. P2SMR Register (Group/Bank 0Fh, Register 1)

Bit

Bit/Field

P27RS P26RS P25RS P24RS P23RS P22RS

P21RS

P20RS

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

76543210
(by bit)

Port 2 Stop Mode
Recovery

R/W

1
0

Recovery Source
Not

Table 50. P5SMR Register (Group/Bank 0Fh, Register 5)

Bit

Bit/Field

P57RS P56RS P55RS P54RS P53RS P52RS

P51RS

P50RS

R/W

R/W

Reset

R = Read, W = Write, X = Indeterminate
Bit
Position

Bit/Field

R/W

Value

Description

76543210
(by bit)

Port 5 Stop Mode
Recovery

R/W

1
0

Recovery Source
Not

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

Electrical Characteristics

This section covers the absolute maximum ratings, standard test conditions, DC
characteristics, and AC characteristics.

Absolute Maximum Ratings

Table 51 lists the absolute maximum ratings.

Stresses greater than those listed in the preceding table can cause permanent
damage to the device. This rating is a stress rating only. Functional operation of
the device at any condition above those indicated in the operational sections of
these specifications is not implied. Exposure to absolute maximum rating condi-
tions for an extended period can affect device reliability.

Table 51. Absolute Maximum Ratings

Symbol

Description

Min

Max

Units

MAX

Supply Voltage (*)

0.3

+7.0

STG

Storage Temp.

+150

Oper. Ambient Temp.

RAM

Minimum RAM Voltage

1.0 V**

Note:

*Voltage on all pins with respect to GND.
See "Ordering Information" on page 84.
** Estimated value, not tested.

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

Table 52. DC Characteristics for the Z86L97X (Mask Only)

Symbol

Parameter

Min

Max

Units

Comments

Power Supply Voltage

2.3

5.5

Clock Input High Voltage

2.3 V
5.5 V

0.8Vdd
0.8Vdd

Vdd+0.3
Vdd+0.3

V
V

Driven by Ext. clock
generator

Clock Input Low Voltage

2.3 V
5.5 V

Vss0.3
Vss0.3

0.2Vdd
0.2Vdd

Driven by Ext. clock
generator

Input High Voltage

2.3 V
5.5 V

0.7Vdd
0.7Vdd

Vdd+0.3
Vdd+0.3

V
V

Input Low Voltage

2.3 V
5.5 V

Vss0.3
Vss0.3

0.2Vdd
0.2Vdd

V
V

OH1

Output High Voltage
Regular I/O

2.3 V
5.5 V

2.0
5.0

V
V

0.5 mA

2.3 V
5.5 V

1.9
5.0

V
V

1.2 mA

OH2

High Drive Pins (P54, P55, P56, P57)

2.3 V
5.5 V

1.9
5.1

V
V

3 mA

2.3 V
5.5 V

1.7
4.7

V
V

5 mA

OL1

Regular I/O
Output low voltage

2.3 V
5.5 V

0.4 V
0.4 V

V
V

2 mA

2.3 V
5.5 V

0.8 V
0.8 V

V
V

4 mA

OL2

High Drive Pins (P54, P55, P56, P57)

2.3 V
5.5 V

0.4 V
0.4 V

V
V

4 mA

2.3 V
5.5 V

0.8 V
0.4 V

V
V

7 mA

CCO

Controlled Current Output (P43)

2.3 V
5.5 V

70
70

120
120

mA
mA

Vout = 1.2 V to VDD at
room temperature (see
Figure 14)

Input Leakage

2.3 V
5.5 V

1
1

Vin=0 V, Vdd
Vin=0 V, Vdd

Supply Current

2.3 V
5.5 V
2.3 V
5.5 V

3
8
250
850

mA
mA

at 8 MHz
at 8 MHz
at 32 KHz
at 32 KHz

CC1

Standby Current (Halt Mode)

2.3 V
5.5 V

2
5

mA
mA

Vin=0 V, Vdd
at 8 MHz

CC2

Standby Current (STOP Mode)

2.3 V
5.5 V

8
25

Vin=0 V, Vdd
P43=1 or high impedance

CC2

Standby Current (STOP Mode)

5.5 V

at 30

Standby Current (Low Voltage)

Vdd Low-Voltage Protection

2.2

Low voltage protection is
also known as brownout.
Typical is around 1.7 V at
room temperature.

Low-Battery Detection

3.0

Typical is around 2.4 V at
room temperature.

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

AC Characteristics

Table 53 lists the AC characteristics.

Table 53. AC Characteristics

No. Symbol

Parameter

VDD

Min

Max

Units

TpC

Input Clock Period

2.3 V
5.5 V

120
120

DC
DC

TrC, TfC

Clock Input Rise and Fall Times

2.3 V
5.5 V

25 ns
25 ns

TwC

Input Clock Width

2.3 V
5.5 V

5.0
5.0

ns
ns

TwTinL

Timer Input Low Width

2.3 V
5.5 V

2TPC
2TPC

TwTinH

Timer Input High Width

2.3 V
5.5 V

2
2

TpC
TpC

TpT1in

Timer 1 Input Period

2.3 V
5.5 V

8
8

TpC
TpC

TrTin, TfTin Timer Input Rise and Fall Time

2.3 V
5.5 V

100
100

ns
ns

TwIL

Interrupt Request Low Time

2.3 V
5.5 V

100
70

ns
ns

TwIH

Interrupt Request Input High Time 2.3 V

5.5 V

5
5

TpC
TpC

Twsm

Stop-Mode Recovery Width Spec

2.3 V
5.5 V

12
12

ns
ns

Twdt

Watch-Dog Timer Time Out

2.3 V
5.5 V

25
10

ms
ms

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

Figure 35. 40-Pin PDIP

Design Considerations

The Z8 uses a Pierce oscillator with an internal feedback circuit. The advantages
of this circuit are low cost, large output signal, low-power level in the crystal, stabil-
ity with respect to V

and temperature, and low impedances (not disturbed by

stray effects.)

One drawback is the requirement for high gain in the amplifier to compensate for
feedback path losses. Traces connecting crystal, capacitors, and the Z8 oscillator
pins must be as short and wide as possible. Short and wide traces reduce para-
sitic inductance and resistance. The components (capacitors, crystal, and resis-
tors) must be placed as close as possible to the oscillator pins of the Z8.

The traces from the oscillator pins of the integrated circuit (IC) and the ground
side of the lead capacitors must be guarded from all other traces (clock, V

, and

system ground) to reduce cross-talk and noise injection. Guarding the traces is
usually accomplished by keeping other traces and system ground trace planes
away from the oscillator circuit and by placing a Z8 device V

ground ring around

the traces/components. The ground side of the oscillator lead capacitors must be
connected to a single trace to the Z8 V

(GND) pin. It must not be shared with

any other system ground trace or components except at the Z8 device V

pin.

Not sharing the ground side of the oscillator lead capacitors is to prevent differen-
tial system ground noise injection into the oscillator.

Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

PS010504-1002

P R E L I M I N A R Y

Ordering Information

For fast results, contact your local ZiLOG sale offices for assistance in ordering
part(s). Updated information is available on the ZiLOG website:

HTTP

://

WWW

LOG.

COM

Precharacterization Product

The product represented by this document is newly introduced and ZiLOG has not
completed the full characterization of the product. The document states what
ZiLOG knows about this product at this time, but additional features or nonconfor-
mance with some aspects of the document might be found, either by ZiLOG or its
customers in the course of further application and characterization work. In addi-
tion, ZiLOG cautions that delivery might be uncertain at times, due to start-up yield
issues.

ZiLOG, Inc.

532 Race Street

San Jose, CA 95126-3432

Telephone: (408) 558-8500

FAX: 408 558-8300

Internet:

HTTP

://

WWW

LOG.

COM

Part

PSI

Memory

Description

Z86D99 (OTP)

Z86D990PZ008SC
Z86D990HZ008SC
Z86D991PZ008SC
Z86D991SZ008SC

32K OTP
32K OTP
32K OTP
32K OTP

40-pin PDIP
48-pin SSOP
28-pin PDIP
28-pin SOIC

Z86L97 (Mask ROM)

Z86L972PZ008SC
Z86L972HZ008SC
Z86L973PZ008SC
Z86L973HZ008SC
Z86L974PZ008SC
Z86L974HZ008SC

4K ROM
4K ROM
8 ROM
8K ROM
16K ROM
16K ROM

40-pin PDIP
48-pin SSOP
40-pin PDIP
48-pin SSOP
40-pin PDIP
48-pin SSOP

Emulator

Z86L9900100ZEM

Emulator/Programmer

Adapter

Z86D9900100ZDH

48 SSOP Adapter

Evaluation Board

Z86L9900100ZCO

Evaluation Board

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: Z86D991PZ008SC

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: Z86D991PZ008SC